SM8761 Datasheet, PDF (6/11 Pages) Nippon Precision Circuits Inc – Spread Spectrum Clock Generator

SM8761 series
AC Characteristics
SM8761AA
V_DD = 3.3 ± 0.3V, V_SS = 0V, Ta = −20 to +80°C unless otherwise noted.
Parameter
Symbol
Pins
Condition
Rating
Unit
min
typ
max
Clock frequency
Crystal connection
f_in
XT
External clock input^*1
20
–
40
MHz
20
–
108
Output clock rise time^*2
t_r
CLKOUT
C_L = 15pF, V_OL = 0.2V_DD to V_OH =
0.8V_DD transition time
–
2.0
–
ns
Output clock fall time^*2
t_f
CLKOUT
C_L = 15pF, V_OH = 0.8V_DD to V_OL =
0.2V_DD transition time
–
2.0
–
ns
Output clock jitter^*2
Cycle-to-cycle jitter, fin = 33MHz
–
200
–
t_jitter
CLKOUT
Ta = 25°C, C_L = 15pF,
V_O = 0.5V_DD
fin = 75MHz
–
120
–
ps
Output clock duty cycle^*2
Dt
CLKOUT Ta = 25°C, C_L = 15pF, V_O = 0.5V_DD
45
50
55
%
Power-up time^*2,*3
t_p
CLKOUT
–
1
5
ms
*1. When using an external clock input, it is recommended that the clock on XT have 50% duty and V_DD level signal amplitude. Note that the input signal
voltage must not exceed the absolute maximum rating, otherwise it may cause the device to breakdown.
*2. Measured using the circuit in Figure 1 on the NPC standard evaluation board.
*3. The power-up time is the time from when the supply reaches 3.0V after the supply is turned ON until each output clock reaches its designated fre-
quency to within ± 0.1%.
SM8761AB
V_DD = 3.3 ± 0.3V, V_SS = 0V, Ta = −20 to +80°C unless otherwise noted.
Parameter
Symbol
Pins
Condition
Rating
Unit
min
typ
max
Clock frequency
Crystal connection
f_in
XT
External clock input^*1
12
–
32
MHz
12
–
32
Output clock rise time^*2
t_r
CLKOUT
C_L = 15pF, V_OL = 0.2V_DD to V_OH =
0.8V_DD transition time
–
2.0
–
ns
Output clock fall time^*2
t_f
CLKOUT
C_L = 15pF, V_OH = 0.8V_DD to V_OL =
0.2V_DD transition time
–
2.0
–
ns
fin = 12MHz
–
450
–
Output clock jitter^*2
Cycle-to-cycle jitter,
fin = 16MHz
–
200
–
t_jitter
CLKOUT
Ta = 25°C, C_L = 15pF,
V_O = 0.5V_DD
fin = 20MHz
–
300
–
ps
fin = 27MHz
–
180
–
Output clock duty cycle^*2
Dt
CLKOUT Ta = 25°C, C_L = 15pF, V_O = 0.5V_DD
45
50
55
%
Power-up time^*2,*3
t_p
CLKOUT
–
1
5
ms
*1. When using an external clock input, it is recommended that the clock on XT have 50% duty and V_DD level signal amplitude. Note that the input signal
voltage must not exceed the absolute maximum rating, otherwise it may cause the device to breakdown.
*2. Measured using the circuit in Figure 1 on the NPC standard evaluation board.
*3. The power-up time is the time from when the supply reaches 3.0V after the supply is turned ON until each output clock reaches its designated fre-
quency to within ± 0.1%.
X'tal
+
+
DUT
DUT: Device Under Testing
Active Probe
(HP1152A)
Passive Probe
(HP10435A)
Oscilloscope
(Infinium
HP54845A)
Frequency &
Time Interval
Analyzer
(HP5371A)
Figure 1. Measurement circuit
Jitter
Measurement
System
(ASA, M1)
NIPPON PRECISION CIRCUITS INC.—6