SM5160CM Datasheet, PDF (6/7 Pages) Nippon Precision Circuits Inc – Programable PLL Frequency Synthesizer

SM5160CM/DM
Serial data input timing
Stand-by mode
Serial data input timing is shown in figure 5. Data is
read on the rising edge of CLK. The state on DATA
should be changed in sync with the falling edge of CLK.
LE should be LOW while data is being written to the
shift register. When LE goes HIGH, data is transferred
from the shift register to one of the frequency divider
latches.
The stand-by mode is entered by setting VDD1,
VDD2 to 0V while the device is operation.
In the stand-by mode, the amplifiers of XIN, FIN and
N/R counter are stopped. As long as voltage is provide to
VDD3, data written in latch is kept. Exit from this mode
to normal operation, therefore, is made by providing volt-
age to VDD1, VDD2. In this mode, input to FIN must
be done AC coupling, input to XIN must be done AC
coupling or by crystal oscillator. In this mode, DOA,
DOP should be in state of floating.
CLK
DATA
LE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
MSB
LSB
CONTROL
Figure 5. Serial data input
NIPPON PRECISION CIRCUITS-6