SM5160CM Datasheet, PDF (2/7 Pages) Nippon Precision Circuits Inc – Programable PLL Frequency Synthesizer

BLOCK DIAGRAM
SM5160CM/DM
XIN
XOUT
TEST
DATA
CLK
VDD1
1/4
PRESCALER
VDD2
11 or 14 BIT
R COUNTER
14 BIT LATCH
17 BIT SHIFT REGISTER
LEVEL
SHIFTER
PHASE
DETECTOR
LE
FIN
VDD1
16 BIT LATCH
16 BIT N COUNTER
VDD2
LEVEL
SHIFTER
FR
LD
LOCK
DETECTOR
VDD3
CHARGE
PUMP
DOA
DOP
FV
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
XIN
XOUT
VDD3
DOA
DOP
VSS
FIN
VDD1
VDD2
LD
CLK
DATA
LE
FV
FR
TEST
Description
Reference oscillator or external clock input. Internal feedback resistor for AC coupling
Reference oscillator or external clock output. Oscillator is OFF when VDD1 is LOW.
Supply voltage for sections not supplied by VDD1 and VDD2
Output to active lowpass filter. Single-ended, tristate output. Floating when VDD1 is LOW
Output to passive lowpass filter. Single-ended, tristate output Floating when VDD1 is LOW
Ground
Comparison frequency input. Internal feedback resistor for AC coupling
Supply voltage for XIN and FIN amplifiers
Supply voltage for N counter and R counter
Unlock detector output. LOW when PLL is unlocked.
Shift register clock input
Serial data input
Latch enable input
Input frequency divider buffered output. This is level-shifted and input to the phase detector.
Reference frequency divider buffered output. This is level-shifted and input to the phase detector.
Test input. Internal pull-down resistor
NIPPON PRECISION CIRCUITS-2