SM8760CA Datasheet, PDF (5/8 Pages) Nippon Precision Circuits Inc – Spread Spectrum Clock Generator

SM8760CA
FUNCTIONAL DESCRIPTION
Master Clock
The SM8760CA master clock can be generated by the crystal oscillator formed by connecting a crystal (funda-
mental mode) between XT (pin 1) and XTN (pin 2) as shown in Figure 2. Alternatively, an external master
clock can be input directly on XT (pin 1) as shown in Figure 3. If an external clock is input on XT, it is recom-
mended that the clock have 50% duty and V_DD level voltage amplitude. Note that the input clock amplitude
voltage must not exceed the absolute maximum rating, otherwise it may cause the SM8760CA to breakdown.
C1
XT (Pin1)
Oscillator
C2
C1, C2 = 5 to 33pF
XTN (Pin2)
Internal
Circuits
External Clock
Open
XT (Pin1)
Oscillator
XTN (Pin2)
Internal
Circuits
Figure 2. Crystal element connection
Figure 3. External clock input
Function Controls
The SM8760CA power-down and SS modulation ON/OFF functions are controlled using the PDN and ENS
input pins as shown in Table 1.
The power-down function is controlled using the PDN input pin. When PDN (pin 3) is “H”, normal operating
mode is selected. When PDN is “L”, power-down mode is selected. In power-down mode, the CLKOUT and
REFOUT output pins are in a high impedance state.
The SS modulation function is controlled using the ENS input pin. When ENS (pin 4) is “H”, the SS modula-
tion function is ON, and an SS-modulated clock is output on the CLKOUT pin. When ON, the modulation
mode and amplitude is a fixed center spread modulation ± 1.0%. When ENS is “L”, the SS modulation func-
tion is OFF.
Table 1. Function summary
PDN (Pin 3)
H
H
L
L
ENS (Pin 4)
H
L
H
L
Power Down Output (Pin 5, Pin 7)
OFF
Clock out
ON
Hi-Z
SS ON/OFF
ON
OFF
−
SS Mode
Center spread
−
SS Modulation [%]
± 1.0
0.0
−
−
Note. “H” signal represents V_DD level, and “L” represents V_SS level.
SEIKO NPC CORPORATION —5