SM8720AV Datasheet, PDF (4/6 Pages) Nippon Precision Circuits Inc – 3-PLL Multi-Output Clock Generator

SM8720AV
AC Characteristics
f_FIN = 27.0000MHz, V_DD = (V_DD1, V_DD2, V_DD3) = 3.0 ± 0.3V, V_SS = (V_SS1, V_SS2, V_SS3) = 0V,
Ta = −40 to +85°C unless otherwise noted.
Parameter
Symbol
Pins
Conditions
Rating
Unit
min
typ
max
External input clock
frequency
f_FIN
FIN
External clock input
–
27.0000
–
MHz
External clock duty cycle^*1 Dt_FIN
FIN
Ta = 25°C, V_I = 0.5V_DD,
external clock input
45
50
55
%
Output clock rise time^*2
REFOUT
C_L = 25pF, V_OL = 0.2V_DD to
V_OH = 0.8V_DD transition
–
t_r
All outputs excluding C_L = 15pF, V_OL = 0.2V_DD to
REFOUT
V_OH = 0.8V_DD transition
–
–
3.0
ns
–
4.0
ns
Output clock fall time^*2
REFOUT
C_L = 25pF, V_OH = 0.8V_DD to
V_OL = 0.2V_DD transition
–
t_f
All outputs excluding C_L = 15pF, V_OH = 0.8V_DD to
REFOUT
V_OL = 0.2V_DD transition
–
–
3.0
ns
–
4.0
ns
REFOUT
Ta = 25°C, C_L = 25pF,
V_O = 0.5V_DD
–
140
200
ps
Output clock jitter
(peak-to-peak)^*3,*4
t_jitter
CLK1OUT,
CLK3OUT
Ta = 25°C, C_L = 15pF,
V_O = 0.5V_DD
–
220
350
ps
CLK2OUT
Ta = 25°C, C_L = 15pF,
V_O = 0.5V_DD
–
220
500
ps
Output clock duty cycle
REFOUT^*2,*5
Ta = 25°C, C_L = 25pF,
V_O = 0.5V_DD
Dt
All outputs excluding
REFOUT^*2
Ta = 25°C, C_L = 15pF,
V_O = 0.5V_DD
45
50
55
%
45
50
55
%
Power-up time^*2,*6
t_P
All outputs excluding
REFOUT
–
1
5
ms
*1. When using an external clock input, it is recommended that FIN duty cycle = 50%, clock signal amplitude = V_DD level. Note that the input signal
voltage amplitude should not exceed the absolute maximum rating, otherwise the device may be damaged.
*2. Measured using the circuit shown in figure 1 on the NPC standard evaluation board.
*3. Measured using the circuit shown in figure 2 on the NPC standard evaluation board.
*4. Measured using master clock input on FIN with ≤80ps (peak-to-peak) jitter.
*5. Measured using master clock input on FIN with duty cycle = 50%, clock signal amplitude = V_DD level.
*6. The power-up time is the time from supply OFF/ON transition or enable LOW/HIGH transition until each output clock reaches its designated
frequency to within ±0.1%.
27MHz
DUT
Active Probe
(HP1152A)
DUT:Device under test
Passive Probe
(HP10435A)
Oscilloscope
(Infinium
HP54845A)
Frequency &
Time Interval
Analyzer
(HP5371A)
Figure 1. Measurement circuit 1
27MHz
DUT
Active Probe
(HP54701A)
DUT:Device under test
Oscilloscope
(HP54720D
+HP54721A)
Jitter
Measurement
System
(ASA, M1)
Figure 2. Measurement circuit 2
NIPPON PRECISION CIRCUITS INC.—4