SM5901AF Datasheet, PDF (3/31 Pages) Nippon Precision Circuits Inc – compression and non compression type anti-shock memory controller with built-in 1M DRAM

Pin description
SM5901AF
Pin number
Pine name
I/O
Function
Setting
H
L
1
VDD2
-
VDD supply pin
2
UC1
Ip/O
Microcontroller interface extension I/O 1
3
UC2
Ip/O
Microcontroller interface extension I/O 2
4
UC3
Ip/O
Microcontroller interface extension I/O 3
5
UC4
Ip/O
Microcontroller interface extension I/O 4
6
VSS2
-
Ground
7
NTEST1
Ip
Test pin
Test
8
NTEST2
Ip
Test pin
Test
9
CLK
I
16.9344 MHz clock input
10
VSS1
-
Ground
11
YSRDATA
I
Audio serial input data
12
YLRCK
I
Audio serial input LR clock
Left channel Right channel
13
YSCK
I
Audio serial input bit clock
14
ZSCK
O
Audio serial output bit clock
15
ZLRCK
O
Audio serial output LR clock
Left channel Right channel
16
ZSRDATA
O
Audio serial output data
17
YFLAG
I
Signal processor IC RAM overflow flag
Overflow
18
YFCLK
I
Crystal-controlled frame clock
19
YBLKCK
I
Subcode block clock signal
20
NRESET
I
System reset pin
Reset
21
ZSENSE
O
Microcontroller interface status output
22
VDD1
-
VDD supply pin
23
YDMUTE
I
Forced mute pin
Mute
24
YMLD
I
Microcontroller interface latch clock
25
YMDATA
I
Microcontroller interface serial data
26
YMCLK
I
Microcontroller interface shift clock
27
NTEST4
Ip
Test pin
Test
28
NCAS2
O
DRAM CAS control
29
D2
I/O
DRAM data input/output 2
30
D3
I/O
DRAM data input/output 3
31
D0
I/O
DRAM data input/output 0
32
D1
I/O
DRAM data input/output 1
33
NWE
O
DRAM WE control
34
NRAS
O
DRAM RAS control
35
NTEST4
Ip
Test pin
Test
36
A8
O
DRAM address 8
37
A7
O
DRAM address 7
38
A6
O
DRAM address 6
39
A5
O
DRAM address 5
40
A4
O
DRAM address 4
41
A0
O
DRAM address 0
42
A1
O
DRAM address 1
43
A2
O
DRAM address 2
44
A3
O
DRAM address 3
Ip : Input pin with pull-up resistor Ip/O : Input/Output pin (With pull-up resistor when a input mode)
And in case that only internal 1M DRAM is used, 28, 33, 34, 36 to 44 pin are high impedance, and 29 to 32 pin are input pull up mode.