SM9103M Datasheet, PDF (12/14 Pages) Nippon Precision Circuits Inc – DVDRAM Head Amplifier LSI

SM9103M
Tracking Signal Processor
The tracking stage generates the push-pull tracking Table 2. TSUB gain setting
error signal and output signal for DPD servo, as well
as a push-pull sum signal used as an auxiliary signal.
TG3
TG2
TG1
TG0
0
0
0
0
The [(A + B) − (C + D)] signal from the com-
mon-data front-end amplifier and signal processor
0
0
0
1
block is sent to the gain switching block. The gain
0
0
1
0
switching block amplifies the difference signal using
0
0
1
1
one of 16 preset gain settings in 2 dB steps to form a
push-pull signal output on TSUB. A feedback resis-
0
1
0
0
tor connected to TSUBB is used to ensure gain set-
0
1
0
1
ting stability. The gain of the gain switching block is
0
1
1
0
controlled by serial interface control bits as shown in
table 2.
0
1
1
1
Each signal from T1, T2, T3, T4 is buffered and then
1
0
0
0
output on DPDA, DPDB, DPDC, DPDD, respec-
1
0
0
1
tively, for DPD servos.
1
0
1
0
The auxiliary signal is generated from the push-pull
1
0
1
1
sum signal (A + B + C + D). This signal is buffered
1
1
0
0
(TAB) and output on TADD. A feedback resistor
connected to TADDB is used to ensure gain setting
1
1
0
1
stability.
1
1
1
0
1
1
1
1
1. Default is 0 dB
Focus Signal Processor
The focus stage generates the focus error signal from Table 3. FSUB gain setting
the focus PD, and a sum signal. The weak focus PD
current signals (F1, F2) are input to the front-end
FG3
FG2
FG1
FG0
amplifier and then current-to-voltage converted at
0
0
0
0
fixed gain.
0
0
0
1
The front-end amplifier output is sent to the signal
0
0
1
0
processor block where the focus error signal (F1 −
0
0
1
1
F2) and the sum signal (F1 + F2) are generated.
0
1
0
0
The focus error signal is sent to the gain switching
block. The gain switching block amplifies the differ-
0
1
0
1
ence signal using one of 16 preset gain settings in 2
0
1
1
0
dB steps with output on FSUB. A feedback resistor
0
1
1
1
connected to FSUBB is used to ensure gain setting
stability. The gain of the gain switching block is con-
1
0
0
0
trolled by serial interface control bits as shown in
1
0
0
1
table 3.
1
0
1
0
The sum is buffered and output on FADD. A feed-
1
0
1
1
back resistor connected to FADDB is used to ensure
1
1
0
0
gain setting stability.
1
1
0
1
1
1
1
0
1
1
1
1
1. Default is 0 dB
Gain (dB)¹
+14
+12
+10
+8
+6
+4
+2
0
−2
−4
−6
−8
−10
−12
−14
−16
Gain (dB)¹
+14
+12
+10
+8
+6
+4
+2
0
−2
−4
−6
−8
−10
−12
−14
−16
NIPPON PRECISION CIRCUITS—12