SM9103M Datasheet, PDF (11/14 Pages) Nippon Precision Circuits Inc – DVDRAM Head Amplifier LSI

SM9103M
FUNCTIONAL DESCRIPTION
Serial Interface
The SM9103M uses a serial interface comprising 2
ports to control and set TSUB/FSUB output gain
switching, sleep mode to reduce current consump-
Table 1. Port address and bit configuration¹
tion, and TSUB/FSUB offset correction. The address
and bit configuration of each port is shown in table 1.
Bit number
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Data
Address
MSB
LSB
TG3 TG2 TG1 TG0 FG3 FG2 FG1 FG0 × LOW LOW LOW LOW LOW ×
×
SL1 CS1 –
–
–
–
–
–
× LOW LOW LOW LOW HIGH ×
×
1. × = don’t care, – = unassigned
TG3 to TG0: TSUB gain set bits. Default = 0111 (0 dB)
FG3 to FG0: FSUB gain set bits. Default = 0111 (0 dB)
SL1: sleep mode set bit. Sleep mode when 1, normal operation when 0. Default = 0.
CS1: offset correction control. Offset correction when 1, normal operation when 0. Default = 0.
Serial data is input on SDATA with the LSB first in
sync with the falling edge of the SCLK clock. After
the 16th SCLK falling edge and 16 bits of valid data
has been input, the SDATA n-channel open-drain
output goes LOW to perform the function of an
acknowledge signal.
If the number of SCLK cycles which occur when
SENB (serial interface enable) is HIGH is less than
16, the received data is ignored and the internal port
is not updated. If the number of SCLK cycles is
greater than 16, the data is still considered value up
to the 16th SCLK falling edge, the data is latched
into the internal port, and the acknowledge signal is
output. The acknowledge signal is held until SENB
goes LOW again.
Data Signal Processor
This stage creates the data signal and ID signal for
output. The weak current from the tracking PD cells
(T1, T2, T3, T4) are input to the front-end amplifier
where the signals are current-to-voltage converted at
fixed gain.
The gain setting is controlled by pins WRITE and
MODE. WRITE switches between read/write, and
MODE switches the gain between values corre-
sponding to high-reflectivity and low-reflectivity
discs. These signals control the settings for RAM
(low-reflectivity disc) read/write and ROM
(high-reflectivity disc) read.
The front-end amplifier outputs are processed by the
signal processor block to generate intermediate sig-
nals. The data signal, (A + B + C + D), is converted
to a difference signal by a differential output buffer
and output on DATAP and DATAN. The ID signal,
generated from the difference between 2 signals, (A
+ B) and (C + D), is converted to a difference signal
by a differential output buffer and output on CAPAP
and CAPAN. The data signal (DATAP, DATAN) and
ID signal (CAPAP, CAPAN) DC components are
removed using output stage capacitive networks.
T1, T2, T3 and T4 have a hold function to provide
the appropriate reverse bias required by the tracking
PD to ensure the data read bandwidth.
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