SM5852DS Datasheet, PDF (12/14 Pages) Nippon Precision Circuits Inc – Digital Audio Processor LSI

SM5852DS
INPUT/OUTPUT TIMING
Input Timing
LRCI
BCKI
DI
MSB
Lch
LSB
MSB
Rch
LSB
There must be a minimum of 16 BCKI clock cycles to read in a single word of data.
Data on DI is input in sync with the falling edge of BCKI in 16-bit serial, MSB first, 2s complement format.
Output Timing
LRCO
BCKO
DOUT
,,,
MSB
Lch
Shaded areas represent intervals of invalid data.
L_,,,SB_,,,
MSB
Rch
LSB_,,,
NIPPON PRECISION CIRCUITS—12