SM5950AM Datasheet, PDF (10/20 Pages) Nippon Precision Circuits Inc – Asynchronous Sample Rate Converter

SM5950AM
FUNCTIONAL DESCRIPTION
Input Interface Settings (IMOD0, IMOD1, IISI)
Input data format
2s-complement, MSB-first, L/R alternating serial data
IMOD0
L
H
L
H
H or L
IMOD1
L
L
H
H
H or L
IISI
Format
L
16-bit MSB-first right-justified
L
20-bit MSB-first right-justified
L
24-bit MSB-first right-justified
L
MSB-first left-justified (leading 16 bits valid data)
H
IIS (leading 16 bits valid data)
Note: L = Low input level, H = high input level
Input timing
The input timing for each input format is shown in figures 4 to 8.
Output System Clock (SCKO)
A clock with frequency 512 times the output sampling frequency (fso) must be input on SCKO. In master
mode, the LRCO and BCKO output clocks are derived from the input clock on SCKO. It also functions as the
internal computation circuit system clock.
Output Interface Settings (OMOD0, OMOD1, IISO, THROU, SLAVE)
Output data format
2s-complement, MSB-first, L/R alternating serial
OMOD0
OMOD1
IISO
L
L
L
H
L
L
L
H
L
H
H
L
H or L
H or L
H
Note: L = Low input level, H = high input level
Output mode select
Format
16-bit MSB-first right-justified
20-bit MSB-first right-justified
24-bit MSB-first right-justified
MSB-first left-justified (16-bit output)
IIS (16-bit output)
Pin setting
THROU
SLAVE
L
L
H
H
H or L
Mode
Master
Slave
Through
Function
Description
LRCO, BCKO
LRCO and BCKO are derived form SCKO.
Function as outputs
LRCO and BCKO are supplied externally.
Function as inputs
LRCO, BCKO, and DOUT are connected directly to
LRCI, BCKI, and DI inputs.
Function as outputs
Note: DMUTE is valid.
Output timing
The timing for each output format is shown in figures 9 to 13. In slave mode, the input timing of LRCO and
BCKO for each output format is shown in figures 9 to 13. In through mode, the LRCI, BCKI, and DI inputs are
fed through to the outputs regardless of the output data format settings.
NIPPON PRECISION CIRCUITS INC.—10