NJU6676 Datasheet, PDF (31/46 Pages) New Japan Radio – 64-Common X 132-Segment plus 1-Icon Bit Map Type LCD Controller and Driver

NJU6676
PRELIMINARY
5-5) Access to the Display Data RAM and Internal Register.
The NJU6676 is operating as one of pipeline processor by the bus-holder connecting to the internal data bus to
adjust the operation frequency between MPU and the Display Data RAM or Internal Register.
For example, when the MPU reads out the data from the Display Data RAM, the read out data in the data read
cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the
next data read cycle. When the MPU writes the data into the Display Data RAM, the data is held in the bus-
holder, then it is written into the Display Data RAM by the next data write cycle.
Therefore high speed data transmission between MPU and NJU6676 is available because of it is not limited by
the tACC and tDS as display data RAM access time and is limited by the system cycle time (R) or (W).
If the cycle time is not be kept in the MPU operation, NOP should be inserted to the system instead of the
waiting operation.
The read out operation does not read out the data in the pointed address just after the address set operation.
And second read out operation can read out the data correctly from the pointed address.
Therefore, one dummy read operation is required after address setting or write cycle as shown in FIG. 6..
Write timing
MPU signal
Internal signal
WR
Data
Bus holder
WR
N
N
N+1
N+2
N+3
N+1
N+2
N+3
Read timing
MPU signal
WR
RD
Data
Internal signal
WR
RD
Column
address
Bus holder
N
Address
set
N
Dummy
read
n
Data read
n +1
Data read
N
N
Fig.6
N+1
N+2
n
n +1