4PT06AI-S Datasheet, PDF (4/6 Pages) Nell Semiconductor Co., Ltd – Sensitive gate SCRs, 4A

SEMICONDUCTOR
Fig.3 Average and DC on-state current versus
ambient temperature (DPAK)
2.0 ^IT(AV)(A)
1.8
1.6
DC
1.4 ^α=180°
DPAK (S = 0.5cm²)
Device mounted on FR4 with
recommended pad layout
1.2
1.0
0.8
IPAK
0.6
0.4
DC
α=180°
0.2
0.0
0
Tamb(°C)
25
50
75
100
125
Fig.5 Relative variation of gate trigger current
and holding current versus junction
temperature
I_GT,I_H,I_L[Tj] / I_GT,I_H,I_L[Tj=25 C]
2.0
1.8
1.6
1.4
I_GT
1.2
lhand IL
1.0
RGK=1KΩ
0.8
0.6
0.4
Tj(°C)
0.2
0.0
-40 -20 0 20 40 60
80 100 120 140
Fig.7 Relative variation of dV/dt immunity
versus gate-cathode resistance
(typical values)
dV/dt[R_GK] / dV/dt[R_GK=220Ω]
10.00
Tj=125 C
VD=0.67 X VDRM
1.00
0.10
0.01
R_GK(KΩ)
0 200 400 600 800 1000 1200 1400 1600 1800 2000
4PT Series _RRooHHSS
Fig.4 Relative variation of thermal impedance
junction to ambient versus pulse duration
(DPAK)
K=[Zth(j-c)/Rth(j-c)]
1E+0
1E-1
Zth(j-c)
Zth(j-a)
1E-2
1E-3
1E-3
1E-2
1E-1
tp(s)
Device mounted on FR4 with
recommended pad layout
1E+0 1E+1 1E+2 5E+2
Fig.6 Relative variation of holding current
versus gate-cathode resistance
(typical values)
IH[RGK] / IH[RGK=1KΩ
5
Tj=25°C
4
3
2
1
0
1E-2
RGK(KΩ)
1E-1
1E+0
1E+1
Fig.8 Relative variation of dV/dt immunity
versus gate-cathode capacitance
(typical values)
10 ^{dV/dt[CGK] / dV/dt[RGK=220Ω]}
8
6
VD=0.67 X VDRM
Tj=125°C
RGK=220Ω
4
2
0
0 24
C_GK(nF)
6 8 10 12 14 16 18 20 22
www.nellsemi.com
Page 4 of 6