SD-A2980 Datasheet, PDF (12/13 Pages) Nel Frequency Controls,inc – Differential Positive ECL (DPECL 3.3V)

POWER
CONSUMPTION
The Benefits of PECL Technology
PECL differential logic output technology
provides many advantages over more tradi-
tional logic systems, such as CMOS devices,
in high speed systems.
Compared to CMOS, PECL offers the
following benefits:
• PECL output devices deliver greater stability
and reduced skew between outputs because
they inherently have very little difference
between TPLH and TPHL delays. (Clock dri-
ver signals need to be output simultaneously;
delays produce skew and cause signal
integrity problems).
• Lower system jitter is produced by the
lower slew rate of PECL. This technology
has a smaller characteristic transition region
compared to CMOS. PECL produces fast
rise and fall times, which are important for
accurate clocking. Since capacitively coupled
noise currents are I=C dV/dt, CMOS
(2V/ns) will produce six times the noise
of PECL (0.34V/ns) if compared single
ended. If PECL is used differentially, the
advantage is even greater.
• PECL technology eliminates common mode
noise (emissions) by offering differential
inputs and outputs, not available in CMOS.
• Unlike CMOS, PECL further minimizes
noise by using an emitter follower output
stage which does not generate a large cur-
rent spike when switching states. The power
source and ground stay relatively noise free.
CMOS
• PECL technology is a better choice for
driving transmission lines, due to its low
impedance outputs (typically around 6 to
25 ohms) and high impedance inputs (typi-
cally 75 kohms). Its low impedance outputs
are structured as open emitter followers,
allowing for the maximum flexibility to ter-
minate the interconnecting scheme (coax,
twisted pair, PCB traces) appropriately to
minimize reflections.
• PECL can drive 50 ohm transmission lines
directly.
• PECL offers low power supply consumption
at high frequencies (see Fig. 3). The power
consumption stays constant with frequency.
By contrast, CMOS power consumption
starts low at low frequencies, but steadily
rises as the frequency rises. CMOS power
consumption is equal to PECL power
consumption at 65 MHz, after which it
continues to rise sharply.
Fig. 3
PECL technology offers
lower power consumption
at higher frequencies, com-
pared to CMOS technology.
PECL
FREQUENCY