SD-A2980 Datasheet, PDF(10/13 Page) Nel Frequency Controls,inc

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SD-A2980 Datasheet, PDF (10/13 Pages) Nel Frequency Controls,inc – Differential Positive ECL (DPECL 3.3V)

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Clock Generation and

Distribution Component Considerations

1Crystal Oscillator and Logic Selection

Selecting the appropriate crystal oscillator is of

the utmost importance in a high speed application,

since it will provide the clock reference for the

entire clock distribution system.

PECL

Differential

Crystal

Oscillator

Fig. 2

Transmission Load

PECL

Differential

Clock

Distribution

Transmission Load

PECL/CMOS

Translator

PECL/CMOS

Translator

PECL/CMOS

Translator

An effective methodology for

achieving optimum system

performance addresses the

various clock generation

and distribution components

as a complete solution.

Careful selection of the

appropriate components

should take place at the

outset of the project, keep-

ing in mind the componentsâ

interrelation to one another.

Stringent crystal oscillator applications typically

require a frequency stability of Â±20 ppm, fast rise

and fall times of less than 600 picoseconds, low

characteristic jitter, and a Positive Emitter Coupled

Logic (PECL) differential output. The frequency

stability will provide a reliable system reference,

while fast rise and fall times of the waveform will

result in low system jitter. (Although saturating the

transition with fast rise and fall times can introduce

unwanted noise, this noise will be cancelled out by

the use of differential signals.)

Logic Selection: PECL Advantages

Using a PECL logic output provides critical

advantages over CMOS logic output technology

in high speed applications. Unlike CMOS technol-

ogy, PECL technology features a differential out-

put, which is essential for reducing emissions. Yet,

like CMOS, PECL obtains its operating power

from a positive power supply (rather than the neg-

ative power supply voltage that powers ECL logic

technology), enabling the necessary compatibility

with CMOS logic interfaces at the load points.

In addition, PECL technology allows voltage

compensation for further rejection of noise on

the positive voltage supply. All modern PECL

devices contain on-chip bandgap regulators that

provide voltage compensation for noise margins

with variations in the supply voltage, as well as

in junction and ambient temperatures. Because

PECL circuits consist of supply-regulated current

sources which are switched via steering logic to

load resistors, the designer beneï¬ts in two ways:

1) the supply current remains unchanged with

operating frequency

2) AC performance remains unchanged with

voltage, temperature, and frequency

Residual sensitivities of less than 1mV/V for levels,

threshold and noise margins with respect to supply

voltage may be achieved.

For junction temperatures, residual sensitivities

of less than 0.1mV/C are achieved for the same

parameters.

Crystal Oscillator Quality

In addition to ensuring low jitter in the waveform,

designers should be sure that jitter is minimized

in the oscillator itself. This is achieved by selecting

an oscillator containing a very high Q crystal.

Further, the crystal should be tuned to the

oscillator circuit for optimization by the oscillator

manufacturer. Use of a PLL synthesizer in the

oscillator design should be avoided, since jitter

is created by the noise in the phase lock loop.

Other Oscillator Considerations

In PECL systems, all oscillator circuits should

have the power supply well decoupled at the

oscillator. PECL devices need to have this

addressed aggressively, since PECL is referenced

only to the most positive side of the power

supply. Thus, for PECL the Vcc needs to be

as noise-free as possible. Because oscillator

characteristics do change with load impedance

and load bias voltage, it is important to specify

the actual load being used and communicate

this to the oscillator vendor.

The chosen oscillator should have a tight symme-

try of at least 45% minimum and 55% maximum,

and should produce repeatable waveforms to

ensure signal consistency. A ground plane should

be used (see âDesign Subtletiesâ section).

2 Clock Driver/Distribution Considerations

The clock driver should be a PECL differen-

tial deviceâwith differential inputs to receive

the oscillator signals, and differential outputs to

distribute the signals on the PCB. If clock gating

is desired, there should be an Enable pin, probably

single ended.

Another aspect of clock driving should be struc-

tural symmetry of the device, which will reï¬ect in

better overall signal integrity.

Regeneration buffering may be required when trace

length and/or attenuation demand it. It is impor-

tant to structure regeneration such that received sig-

nals have settled out and are not still on their rising

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