UPD705102 Datasheet, PDF (51/80 Pages) NEC – V832TM 32-BIT MICROPROCESSOR

µPD705102
(1) Clock input (X2) timing (when external clock input used)
• µPD705102-143
Parameter
Symbol
Conditions
PLL Magnification
Unit
×6 mode
×8 mode
MIN.
MAX.
MIN.
MAX.
External clock cycle
<1> tCYX
Note 1
42
60
56
80
ns
Note 2
45
60
ns
Note 3
41.6
60
55.5
80
ns
Note 4
45
60
ns
External clock high-level time <2> tXXH
Note 1
16
23
ns
Note 3
15.8
22.75
ns
External clock low-level time
<3> tXXL
Note 1
16
23
ns
Note 3
15.8
22.75
ns
External clock rise time
<4> tXR
5
5
ns
External clock fall time
<5> tXF
5
5
ns
Notes 1. TA = –40 to +85°C, when other than 1/4 is selected as the division ratio of the input clock (CPU
core frequency (when defaulted) = 100 to 143 MHz)
2. TA = –40 to +85°C, when 1/4 is selected as the division ratio of the input clock (CPU core frequency
= 33.3 to 35.8 MHz)
3. TA = –40 to +70°C, when other than 1/4 is selected as the division ratio of the input clock (CPU
core frequency (when defaulted) = 100 to 144 MHz)
4. TA = –40 to +70°C, when 1/4 is selected as the division ratio of the input clock (CPU core frequency
= 33.3 to 36 MHz)
Remark The stability of the input clock is 0.1% of tCYX or lower.
• µPD705102-133
Parameter
Symbol
Conditions
PLL Magnification
Unit
×6 mode
×8 mode
MIN.
MAX.
MIN.
MAX.
External clock cycle
<1> tCYX
Note 1
45
60
60
80
ns
Note 2
45
60
ns
External clock high-level time <2> tXXH
17.5
25
ns
External clock low-level time
<3> tXXL
17.5
25
ns
External clock rise time
<4> tXR
5
5
ns
External clock fall time
<5> tXF
5
5
ns
Notes 1. TA = –40 to +85°C, when other than 1/4 is selected as the division ratio of the input clock (CPU
core frequency (when defaulted) = 100 to 133 MHz)
2. TA = –40 to +85°C, when 1/4 is selected as the division ratio of the input clock (CPU core frequency
= 33.3 MHz)
Remark The stability of the input clock is 0.1% of tCYX or lower.
<1>
<2>
<5>
<4>
0.8 VDDO
X2 (input) 1.4 V
0.2 VDDO
<3>
Data Sheet U13675EJ2V1DS00
51