UPD70F3102-33 Datasheet, PDF (50/82 Pages) NEC – 32-/16-BIT SINGLE-CHIP MICROCONTROLLER

µPD70F3102-33
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Column address setup time
<58>
tASC
(0.5 + wCP) T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA) T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA) T – 10
ns
Column address read time (from
<64>
tRAL
(2 + wCP + wDA) T – 10
ns
RAS↑)
CAS pulse width
<65>
tCAS
(1 + wDA) T – 10
ns
CAS precharge time
<81>
tCP
(1 + wCP) T – 10
ns
RAS hold time for CAS precharge <83> tRHCP
(2.5 + wCP + wDA) T – 10
ns
WE setup time (to CAS↓)
<84>
tWCS
wCP ≥ 1
wCPT – 10
ns
WE hold time (from CAS↓)
<85> tWCH
(1 + wDA) T – 10
ns
Data setup time (to CAS↓)
<86>
tDS
(0.5 + wCP) T – 10
ns
Data hold time (from CAS↓)
<87>
tDH
(1.5 + wDA) T – 10
ns
WE read time (from RAS↑)
<88>
tRWL
wCP = 0
(1.5 + wDA) T – 10
ns
WE read time (from CAS↑)
<89>
tCWL
wCP = 0
(1 + wDA) T – 10
ns
Data setup time (to WE↓)
<90> tDSWE wCP = 0
0.5T – 10
ns
Data hold time (from WE↓)
<91> tDHWE wCP = 0
(1.5 + wDA) T – 10
ns
WE pulse width
<92>
tWP
wCP = 0
(1 + wDA) T – 10
ns
Remarks 1. T = tCYK
2. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
3. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
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Preliminary Data Sheet U13844EJ2V0DS00