UPD75336 Datasheet, PDF (45/68 Pages) NEC – 4-BIT SINGLE-CHIP MICROCOMPUTER

µPD75336
Note 1 ^Mne-
monic
Operands
Bytes ^Machine
Cycles
Operation
Address-
ing Area
Skip Condition
CALL !addr
3
CALLF !faddr
2
RET
1
RETS
1
RETI
1
rp
1
PUSH
BS
2
rp
1
POP
BS
2
2
EI
IE × × ×
2
2
DI
IE × × ×
2
A, PORTn 2
IN*
XA, PORTn 2
PORTn, A 2
OUT*
PORTn, XA 2
HALT
2
STOP
2
NOP
1
RBn
2
SEL
MBn
2
GETI taddr
1
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
2
(SP – 3) ← MBE, RBE, PC13, PC12
*6
PC13–0 ← addr, SP ← SP – 4
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
2
(SP – 3) ← MBE, RBE, PC13, PC12
*9
PC13–0 ← 000 + faddr, SP ← SP – 4
PC11–0 ← (SP) (SP + 3) (SP + 2)
3
MBE, RBE, PC13, PC12 ← (SP + 1)
SP ← SP + 4
PC11–0 ← (SP) (SP + 3) (SP + 2)
3+S MBE, RBE, PC13, PC12 ← (SP + 1)
SP ← SP + 4, then skip unconditionally
Unconditional
PC11–0 ← (SP) (SP + 3) (SP + 2)
3
MBE, RBE, PC13, PC12 ← (SP + 1)
PSW ← (SP + 4) (SP + 5), SP ← SP + 6
1
(SP – 1) (SP – 2) ← rp, SP ← SP – 2
2
(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2
1
rp ← (SP + 1) (SP), SP ← SP + 2
2
MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2
2
IME(IPS.3) ← 1
2
IE × × × ← 1
2
IME(IPS.3) ← 0
2
IE × × × ← 0
2
A ← PORTn
(n = 0–8)
2
XA ← PORTn+1, PORTn
(n = 4, 6)
2
PORTn ← A
(n = 2–8)
2
PORTn+1, PORTn ← XA
(n =4, 6)
2
Set HALT Mode (PCC.2 ← 1)
2
Set STOP Mode (PCC.3 ← 1)
1 No Operation
2
RBS ← n
(n = 0 – 3)
2
MBS ← n
(n = 0, 1, 2, 15)
• TBR Instruction
PC13–0 ← (taddr) 5–0 + (taddr + 1)
-----------------------------------------------------------------------
• TCALL Instruction
-----------------------------
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
3
(SP – 3) ← MBE, RBE, PC13, PC12
*10
PC13–0 ← (taddr) 5–0 ← (taddr + 1)
SP ← SP – 4
-----------------------------------------------------------------------
• Other than TBR and TCALL Instruction
-----------------------------
Depends on the
Execution of an instruction addressed at
referred instruc-
(taddr) and (taddr + 1)
tion
* At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS =15 must be set in advance.
Remarks TBR and TCALL instructons are assembler pseudo instructions for GETI instruction table definition.
Note 1. Instruction Group 2. Interrupt control 3. CPU control
45