UPD780138 Datasheet, PDF (423/558 Pages) NEC – 8-Bit Single-Chip Microcontrollers

CHAPTER 24 REGULATOR
24.1 Outline of Regulator
The 78K0/KE1 includes a circuit to realize constant-voltage operation inside the device. To stabilize the regulator
output voltage, connect the REGC pin to VSS via a capacitor (1 µF: recommended). The output voltage of the
regulator is 3.5 V (TYP.).
The supply voltage and oscillation frequency at which the regulator can be used are as follows.
• Power supply voltage: VDD = 4.0 to 5.5 V
• Oscillation frequency: fX = 2.0 to 8.38 MHz
The regulator of the 78K0/KE1 stops operating in the following cases.
• During the reset period
• In STOP mode
• In HALT mode when the CPU is operating on the subsystem clock and when X1 oscillation is stopped
Figure 24-1 shows the block diagram of the periphery of the regulator.
Figure 24-1. Block Diagram of Regulator Periphery
EVDD system I/O buffer
Internal digital circuits
EVDD
A/D converter
X1, Ring,
sub
oscillator
Flash memory
(µPD78F0134,
78F0138 only)
Regulator
AVREF
Bidirectional
level shifter
REGC
1 µF
VDD VPP
Cautions 1. Directly connect the REGC pin of standard products and (A) grade products to VDD when the
regulator is not used.
2. The regulator cannot be used with (A1) and (A2) grade products. Be sure to connect the
REGC pin of these products directly to VDD.
User’s Manual U16228EJ2V0UD
423