UPD780138 Datasheet, PDF (410/558 Pages) NEC – 8-Bit Single-Chip Microcontrollers

CHAPTER 22 POWER-ON-CLEAR CIRCUIT
22.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection
voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 22-3. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Reset
; The Ring-OSC clock is set as the CPU clock when the reset signal is generated
Checking cause
of reset^{Note 2}
Power-on-clear
; The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
can be identified by the RESF register.
Start timer
(set to 50 ms)
; 8-bit timer H1 can operate with the Ring-OSC clock.
Source: fR (480 kHz (MAX.))/2⁷ × compare value 200 = 53 ms
(fR: Ring-OSC clock oscillation frequency)
Note 1
Check stabilization
of oscillation
Change CPU clock
; Check the stabilization of oscillation of the X1 input clock by using the
OSTC register.
; Change the CPU clock from the Ring-OSC clock to the X1 input clock.
No
50 ms has passed?
(TMIFH1 = 1?)
; TMIFH1 = 1: Interrupt request is generated.
Yes
Initialization
processing
; Initialization of ports
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
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User’s Manual U16228EJ2V0UD