UPD31172 Datasheet, PDF (35/44 Pages) NEC – VRC4172TM COMPANION CHIP FOR VR4121TM

µPD31172
(h) Read timing in EPP1.7 mode
Parameter
DIR1284 setup time
SELECTIN#, AUTOFEED# setup time
IOCHRDY setup time
Timeout generation time
IOCHRDY cancellation time
SELECTIN#, AUTOFEED# cancellation time
CD (7:0) hold time
DIR1284 cancellation time
Symbol
t51
t52
t53
t54
t55
t56
t57
t58
Conditions
Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
MIN.
MAX.
Unit
3T
ns
30
ns
3T
ns
10
µs
3T
ns
3T
ns
0
ns
1T
ns
AD (24:0)
(input)
IOR#
(input)
DATA (31:0) ^Hi-Z
(output)
STROBE#
(output)
SELECTIN#
AUTOFEED#
(output)
CD (7:0)
Hi-Z
(input)
DIR1284
(output)
BUSY
(input)
IOCHRDY
(output)
Hi-Z
Valid data
t52
t56
Valid data
t57
Hi-Z
t51
t58
t54
t53
t55
Data Sheet U14388EJ2V0DS00
35