UPD31172 Datasheet, PDF (30/44 Pages) NEC – VRC4172TM COMPANION CHIP FOR VR4121TM

(10) IEEE1284-compliant parallel interface parameters
(a) Parallel port control signal output
Parameter
Symbol
Parallel interface internal clock frequency
tCLK1284
CD (7:0) output delay time (writing to DATA register)
t1
INIT#, STROBE#, AUTOFEED#, SELECTIN# setup time
t2
DIR1284 setup time
t3
Conditions
Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
µPD31172
MIN.
MAX.
24
30
4T
5T
Unit
MHz
ns
ns
ns
IOW# (input)
t1
CD (7:0)
(I/O)
INIT#, STROBE#,
t2
AUTOFEED#,
SELECTIN#
(I/O)
t3
DIR1284
(output)
(b) Compatible mode using FIFO
Parameter
CD (7:0) setup time
STROBE# pulse width^{Note 1}
BUSY response time
CD (7:0) hold time^{Note 2} (from STROBE# ↑)
CD (7:0) hold time^{Note 2} (from BUSY ↓)
STROBE# setup time^{Note 3}
Symbol
t4
t5
t6
t7
t8
t9
Conditions
MIN.
MAX.
Unit
24 T
ns
24 T
ns
12 T
ns
24 T
ns
0
ns
24 T
ns
Notes 1. When there is no reaction from BUSY at a low level, STROBE# continues to output a low level.
2. Data is held while BUSY is high level.
3. When the FIFO buffer is empty, this signal is held at a high level.
Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.))
CD (7:0)
(output)
STROBE#
(output)
BUSY
(input)
30
Valid data
t4
t5
t7
t8
t6
t9
Data Sheet U14388EJ2V0DS00