UPD72001-11 Datasheet, PDF (31/40 Pages) NEC – MULTI-PROTOCOL SERIAL CONTROLLERS

µPD72001-11, 72001-A8
E/S Timing
CTSA/B, DCDA/B, SYNCA/B
INT
tWML
tDMIQ
tWMH
SYNC Input Timing (external synchronization mode)
STRXCA/B
TRXCA/B
SYNCA/B ^Note
Last Bit of
SYNC Character
1st Bit of
Data Character
tSSYRC
Note SYNCA/B input must be cleared to “0” at the rising edge of RXC two clock cycles after the last bit of the SYNC
character.
XI1 Input Timing
tCYX
XI1
RESET Pulse
RESET
tWRSL
31