UPD72001-11 Datasheet, PDF (3/40 Pages) NEC – MULTI-PROTOCOL SERIAL CONTROLLERS

SPECIFICATIONS
Item
Part number
Supply voltage
System clock frequency
Maximum transfer rate
Process
Internal circuit
Communication protocol
Processing data format
µPD72001-11, 72001-A8
Specifications
µPD72001-11
µPD72001-A8
5 V ±10 %
3.3 V ±0.3 V
11 MHz MAX.
8 MHz MAX. (at TA = –10 to +70 °C)
7.14 MHz MAX. (at TA = –40 to +85 °C)
2.2 Mbps
1.6 Mbps (at TA = –10 to +70 °C)
1.43 Mbps (at TA = –40 to +85 °C)
CMOS
Parallel/serial converter circuit: Full-duplex channel × 2
Transmit buffer : Double
Receive buffer : Quadruple
Interrupt control function
DMA request signal output: 2 for transmission, 2 for reception
Overrun error detection
DPLL
Baud rate generator
Crystal oscillation circuit for transmission/reception clock generation
Self-loopback test function
Standby function
General-purpose I/O pin: 4 pins × 2
Start-stop
synchronization
Character bit length: 5, 6, 7, 8
Stop bit length: 1, 1.5, 2
Clock rate: ×1, ×16, ×32, ×64
Parity generation, check
Framing error detection
Break generation, detection
COP
(Character
Oriented
Protocol)
Operation mode: Mono-sync, Bi-sync, External sync
Character bit length: 5, 6, 7, 8
SYNC character bit length: 6, 8
Character synchronization: Internal/external
BCS (Block Check Sequence) generation, check:
CRC-16
CRC-CCITT
Parity generation, check
SYNC character automatic transmission, detection, rejection
BOP
(Bit Oriented
Protocol)
Operation mode:
HDLC (High-level Data Link Control)
SDLC (Synchronous Data Link Control)
SDLC Loop
Flag transmission, detection
Zero insertion, rejection
Address field detection (1 byte)
FCS (Frame Check Sequence) generation, detection
Short frame detection
Abort automatic transmission, detection
Idle detection
Go Ahead detection
Transmit number data control
Encode/decode of NRZ (Non-Return to Zero)
Encode/decode of NRZI (Non-Return to Zero Inverted)
Encode/decode of FM (Frequency Modulation)
Decode in Manchester mode
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