UPD72042A Datasheet, PDF (24/92 Pages) NEC – LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL

µPD72042A, 72042B
(2) Data read mode
When the C/D pin is set low after register read is selected in control mode, the data read mode is set. In data
read mode, the data in a read register is read on the SO pin upon detecting the falling edge of the SCK pin.
(a) µPD72042A (starting with MSB)
C/D
SCK
SI
A3 A2 A1 A0 1 × × ×
SO
“1”
State
Serial clock counter
reset pointer
Control mode
(selection of register read)
(b) µPD72042B (starting with LSB)
D7 D6 D5 D4 D3 D2 D1 D0
Data read mode
C/D
SCK
SI
× × × 1 A0 A1 A2 A3
SO
“1”
State
Control mode
(selection of register read)
Serial clock counter
reset pointer
D0 D1 D2 D3 D4 D5 D6 D7
Data read mode
Caution When the C/D pin is set high in data read mode, the serial clock counter is reset. Therefore, the
remaining bits of the byte cannot be read; at the next falling edge, read is performed starting from
the next byte in the case of RBF, or from the first bit for other registers.
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DATA SHEET S13990EJ2V0DS00