UPD17134A Datasheet, PDF (23/292 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER

1.3 BLOCK DIAGRAM
CHAPTER 1 GENERAL DESCRIPTION
VDD
POWER-ON/
POWER-DOWN
RESET
P0A0
P0A1
P0A2
P0A3
P0B0
P0B1
P0B2
P0B3
P0C0/ADC0
P0C1/ADC1
P0C2/ADC2
P0C3/ADC3
P0D0/SCK
P0D1/SO
P0D2/SI
P0D3/TM0OUT
GND
P0A
(CMOS)
P0B
(CMOS)
P0C
(CMOS)
A/D
Con-
verter
P0D
(N-ch)
TM0
Serial
Inter-
face
IRQSIO
RF
RAM
112 × 4 bits
SYSTEM REG.
ALU
Clock
divider
System clock
generator
XIN _(CLK)Note2
XOUT
fX/2^N CPU CLOCK CLK STOP
INT
Interrupt
controller
IRQTM0
IRQTM1
IRQBTM
IRQSIO
AC
ZEROCROSS
detector
IRQBTM
Basic interval timer
fX/2^N
IRQTM1
Timer 1
fX/2^N
IRQTM0
Timer 0
fX/2^N
Note1
ROM/
One-Time
PROM
Instruction
decoder
Program counter
Stack^Note2
P1A
(N-ch)
P1B
P1A0
P1A1
P1A2
P1A3
P1B0
(VPP)
RESET
Remarks 1.
2.
The terms CMOS and N-ch in square brackets indicate the output form of the port.
CMOS : CMOS push-pull output
N-ch : N-channel open-drain output (Each pin can contain pull-up resistor bit-wise as specified
using a mask option.)
The devices in parentheses are effective only in the case of program memory write/verify mode of
the µPD17P136A and µPD17P137A.
Notes 1.
2.
The ROM (or PROM) capacity of each product is as follows:
1024 × 16 bits : µPD17134A, 17135A
2048 × 16 bits : µPD17136A, 17137A, 17P136A, 17P137A
The stack capacity of each product is as follows:
5 × 10 bits : µPD17134A, 17135A
5 × 11 bits : µPD17136A, 17137A
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