UPD17134A Datasheet, PDF (200/292 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER

CHAPTER 17 RESET
Figure 17-1. Reset Block Configuration
1
Internal bus
2
RF : 10H
000
PDRESEN
Clear
Power-down reset circuit
VDD
Power-on reset circuit
3
4
Internal reset signal
5
6
Mask option
7
RESET
8
17.2 RESETTING
9
Operation when system reset is caused by the RESET pin is shown in the figure below.
If the RESET pin is set from low to high, system clock oscillation starts and an oscillation stabilization wait occurs
with the timer 1. Program execution starts from address 0000H.
10
If power-on reset is used, the reset signals shown in Figure 17-2 are internally generated. Operation is the same
as that when reset is caused externally by the RESET pin.
11
At watchdog timer overflow reset or stack overflow and underflow reset, oscillation stabilization wait time (WAIT)
does not occur. Operation starts from address 0000H after initial statuses are internally set.
12
Figure 17-2. Reset Operation
13
RESET
14
15
TM1EN
16
TM1RES
17
Operating mode
Reset
WAIT^Note
Operating mode
18
Note This is oscillation stabilization wait time. Operating mode is set when timer 1 counts system clocks (fCC)
512 × 256 counts approx. 65 ms at fCC = 2 MHz).
19
20
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