UPD720122 Datasheet, PDF (22/82 Pages) NEC – MOS Integrated Circuit

µPD720122
(2) CPU bus write operation
Symbol
T11
T12
T13
T14
T15
T16
T17
T18
T19
Parameter
Write cycle time
Address setup time (WRB↓)
Chip select setup time (WRB↓)
Write command width
Address hold time (WRB↑)
Chip select hold time (WRB↑)
WRB inactive time
Input data setup time
Input data hold time
Min.
Typ.
Max.
Unit
68
∞
ns
5
∞
ns
5
∞
ns
34
∞
ns
5
∞
ns
5
∞
ns
34
∞
ns
10
∞
ns
0
∞
ns
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
CPU bus write timing
A7 to A1
t12
CSB
t13
WRB
t11
VALID
t14
t15
t16
t17
RDB
High level
D15 to D0
t18
t19
VALID
22
Data Sheet S16685EJ2V0DS