UPA1720 Datasheet, PDF (2/8 Pages) NEC – SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE

µ PA1720
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Drain to Source On-state Resistance
RDS(on)1 VGS = 10 V, ID = 4.0 A
20.0 25.0 mΩ
RDS(on)2 VGS = 4.5 V, ID = 4.0 A
25.5 33.0 mΩ
RDS(on)3 VGS = 4.0 V, ID = 4.0 A
29.0 38.0 mΩ
Gate to Source Cut-off Voltage
VGS(off) VDS = 10 V, ID = 1 mA
1.5 2.0 2.5 V
Forward Transfer Admittance
| yfs | VDS = 10 V, ID = 4.0 A
3.0 7.0
S
Drain Leakage Current
IDSS
VDS = 30 V, VGS = 0 V
10 µA
Gate to Source Leakage Current
IGSS
VGS = ±16 V, VDS = 0 V
±10 µA
Input Capacitance
Ciss
VDS = 10 V
800
pF
Output Capacitance
Coss
VGS = 0 V
250
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
96
pF
Turn-on Delay Time
td(on)
ID = 4.0 A
20
ns
Rise Time
tr
VGS(on) = 10 V
80
ns
Turn-off Delay Time
td(off)
VDD = 15 V
40
ns
Fall Time
tf
RG = 10 Ω
40
ns
Total Gate Charge
QG
ID = 8 A
14
nC
Gate to Source Charge
QGS
VDD = 24 V
2.3
nC
Gate to Drain Charge
QGD
VGS = 10 V
3.6
nC
Body Diode Forward Voltage
VF(S-D) IF = 8 A, VGS = 0 V
0.86
V
Reverse Recovery Time
trr
IF = 8 A, VGS = 0 V
30
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/ µs
40
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
IAS
ID
VDD
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
RG
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
RL
VDD
VGS
VGS
Wave Form
10 %
0
ID
ID
Wave Form
0 ^{10 %}
VGS(on)
90 %
ID
90 %
90 %
10 %
td(on)
tr td(off)
tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet G13888EJ2V0DS00