UPD23C256112A Datasheet, PDF (19/32 Pages) NEC – NAND INTERFACE 256M-BIT MASK-PROGRAMMABLE ROM

Sequential Read Cycle Timing Chart (2)
(In case of read mode (2))
CLE
tCLS
/CE
tCS
/WE
ALE
tCLH
tCH
tCS
tWC
tALH
tALS tWP tWH
tR
tALH
tAR2
tRR
tRC
tRC
/RE
I/O0 to I/O7
tDS tDH
01H
R, /B
tDS
A0 to A7
tWB
tDS
tDS
A9 to A16 A17 to A24
High-Z
tDH
tDH
tDH
tRP tREH
tRHZ
DOUT
256+N
tREA
DOUT
256+N+1
Access
page M
Output page M data
Remark Start address (SA) specification when read is performed with command 01H. N: 0 to 255
tR
tRR
DOUT
High-Z
527
tRB
High-Z
DOUT
DOUT
0
1
Access
page M+1
Output page
M+1 data