UPD23C256112A Datasheet, PDF (1/32 Pages) NEC – NAND INTERFACE 256M-BIT MASK-PROGRAMMABLE ROM

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD23C256112A
NAND INTERFACE
256M-BIT MASK-PROGRAMMABLE ROM
Description
The µPD23C256112A is a 256 Mbit NAND interface programmable mask read-only memory that operates with a
single power supply. The memory organization consists of (512 + 16 (Redundancy)) bytes x 32 pages x 2,048 blocks.
The µPD23C256112A is a serial type mask ROM in which addresses and commands are input and data output
serially via the I/O pins.
The µPD23C256112A is packed in 48-pin PLASTIC TSOP(I).
Features
• Word organization
(33,554,432 + 1,048,576^Note) words by 8 bits
• Page size
(512 + 16^Note) by 8 bits
• Block size
(16,384 + 512^Note) by 8 bits
Note Underlined parts are redundancy.
Caution Redundancy is not programmable parts and is fixed to all FFH.
• Operation mode
READ mode (1), READ mode (2), READ mode (3), RESET, STATUS READ, ID READ
• Operating supply voltage : VCC = 3.3 ± 0.3 V
• Access Time
Memory cell array to starting address : 7 µs (MAX.)
Read cycle time
: 50 ns (MIN.)
/RE access time
: 35 ns (MAX.)
• Operating supply current
During read
: 30 mA (MAX.) (50 ns cycle operation)
During standby (CMOS) : 100 µA (MAX.)
Ordering Information
Part Number
µPD23C256112AGY-xxx-MJH
µPD23C256112AGY-xxx-MKH
(xxx : ROM code suffix No.)
Package
48-pin PLASTIC TSOP(I) (12x18) (Normal bent)
48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15902EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
The mark 5 shows major revised points.
Printed in Japan
©
2001