UPD753012 Datasheet, PDF (17/80 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER

µPD753012, 753016, 753017
5. MEMORY CONFIGURATION
• Program memory (ROM) ............... 12288 × 8 bits (µPD753012)
............... 16384 × 8 bits (µPD753016)
............... 24576 × 8 bits (µPD753017)
• Data memory (RAM)
· Data area …1024 words × 4 bits (000H to 3FFH)
· Peripheral hardware area…128 × 4 bits (F80H to FFFH)
Figure 5-1. Program Memory Map (1/3)
(a) µPD753012
0000H
0002H
0004H
0006H
0008H
000AH
000CH
0020H
007FH
0080H
07FFH
0800H
7
MBE
MBE
MBE
MBE
MBE
MBE
MBE
65
0
RBE Internal reset start address (high-order 6 bits)
Internal reset start address (Iow-order 8 bits)
RBE INTBT/INT4 start address (high-order 6 bits)
INTBT/INT4 start address (Iow-order 8 bits)
RBE INT0 start address
(high-order 6 bits)
INT0 start address
(Iow-order 8 bits)
RBE INT1 start address
(high-order 6 bits)
INT1 start address
(Iow-order 8 bits)
RBE INTCSI start address
(high-order 6 bits)
INTCSI start address
(Iow-order 8 bits)
RBE INTT0 start address
(high-order 6 bits)
INTT0 start address
(Iow-order 8 bits)
RBE INTT1, INTT2 start address (high-order 6 bits)
INTT1, INTT2 start address (Iow-order 8 bits)
GETI instruction reference table
CALLF !faddr
instruction
entry address
Branch address of
BR BCXA, BR BCDE,
BR !addr1, BRA !addr1^Note
or CALLA !addr1^Note
instruction
BRCB !caddr
instruction
branch address
CALL !addr instruction
subroutine entry address
BR $addr instruction
relative branch address
(–15 to –1, +2 to +16)
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
0FFFH
1000H
1FFFH
2000H
2FFFH
BRCB !caddr instruction
branch address
BRCB !caddr instruction
branch address
Note Can be used in Mk II mode only.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE, BR PCXA instruction.
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