UPD161831 Datasheet, PDF (15/67 Pages) NEC – 240/244-OUTPUT TFT-LCD SOURCE DRIVER WITH TIMING GENERATOR

µPD161831
4.2 Command Registers
4.2.1 Command register list
Table 4−2 lists the command registers.
However, each register is read default value when invalid data leads in unused of timing generator.
Table 4−2. Command Register List (1/2)
Register
D5 to D0
No.
D5 D4 D3 D2 D1 D0
Register Name
Default
Value
R0
0 0 0 0 0 0 65,000/260,000 color select
00H
Horizontal period valid data input
R1
000001
0AH
start timing
Vertical period valid data input
R2
000010
02H
start timing
R3
0 0 0 0 1 1 Horizontal valid pixel data setting
00H
R4
0 0 0 1 0 0 Standby
00H
R5
0 0 0 1 0 1 8-color mode
00H
R6
0 0 0 1 1 0 Setting
02H
R7
− − − − − − Use prohibited (Not used)
−
R8
0 0 1 0 0 0 Amplifier drive period setting
0EH
R9
0 0 1 0 0 1 Quarter data function
00H
R10
0 0 1 0 1 1 Level shifter voltage setting
00H
Common amplitude voltage
R11
001100
0FH
adjustment D/A converter
Common center voltage
R12
001101
35H
adjustment D/A converter
R13, R14 − − − − − − Use prohibited (Not used)
−
R15
0 0 1 1 1 1 Command reset
00H
R16 to R23 − − − − − − Use prohibited (Not used)
−
R24
0 1 1 0 0 0 DC/DC operation setting
00H
R25
0 1 1 0 0 1 DC/DC step setting
16H
R26
0 1 1 0 1 0 DC/DC oscillation setting
15H
R27
0 1 1 0 1 1 Regulator output setting
2AH
R28
0 1 1 1 0 0 LPM setting
00H
R29 to R32 − − − − − − Use prohibited (Not used)
−
R33
1 0 0 0 0 1 DC/DC rise setting
00H
R34, R35 − − − − − − Use prohibited (Not used)
−
Remarks 1. O: Enabled, -: Disabled, ∆1: Only bit 3 disabled, ∆2: Only bit 7 enabled
2. The internal set timing is the timing at which the command is enabled.
C: Enabled when command is set
F: Enabled at beginning of frame
L: Enabled at beginning of line
Timing Generator
Function
Reset
Use Not used Command Hard
O
−
O
−
Internal Set
Timing
F
O
−
O
−
F
O
−
O
−
F
O
−
O
−
C
O
O
O
−
F
O
O
O
−
L
O
∆1
O
Note1 Note2
−
−
−
−
−
O
−
O
−
C
O
O
O
−
F
O
O
O
−
C
O
O
O
−
C
O
O
O
−
C
−
−
−
−
−
O
O
−
−
C
−
−
−
−
−
O
O
O
O
C
O
O
O
O
C
O
O
O
O
C
O
O
O
O
C
O
O
O
O
C
−
−
−
−
−
O
O
O
O
C
−
−
−
−
−
Notes 1. Bit 0 is enabled when line is set. Bit 3 is enabled when frame is set. Al other bits are enabled when command is set.
2. Bits 4 and 5 are enabled when hard reset is performed. All other bits are disabled.
Preliminary Product Information S16269EJ2V0PM
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