UPD703100 Datasheet, PDF (149/185 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 8 PIPELINE
8.3.8 Branch instructions
(1) Conditional branch instructions
[Instructions]
Bcond instructions (BGT, BGE, BLT, BLE, BH, BNL, BL, BNH, BE, BNE, BV, BNV, BN, BP,
BC, BNC, BZ, BNZ, BSA): Except BR instruction
[Pipeline]
(a) When the condition is not realized
1
2
3
4
Conditional branch
instruction
IF
ID
MEM WB
Next instruction
IF
ID
EX
5
6
MEM WB
(b) When the condition is realized
1
2
3
4
5
6
7
Conditional branch
instruction
IF
ID
MEM WB
Next instruction
IF ×
Branch destination instruction
IF
ID
EX MEM WB
IF ×: Instruction fetch that is not executed
[Description]
The pipeline consists of 4 stages, IF, ID, MEM, and WB. However, no operation is performed
in the MEM and WB stages, because memory is not accessed and no data is written to
registers.
(a) When the condition is not realized
The number of execution clocks for the branch instruction is 1.
(b) When the condition is realized
The number of execution clocks for the branch instruction is 2. IF stage of the next
instruction of the branch instruction is not executed. If an instruction overwriting the
contents of PSW occurs immediately before a branch instruction execution, condition wait
time occurs.
(2) Unconditional branch instructions
[Instructions] JR, JARL, BR
[Pipeline]
1
Unconditional branch
instruction
IF
2
ID
Next instruction
IF ×
Branch destination instruction
3
4
5
MEM WB *
IF
ID
EX
6
7
MEM WB
IF ×: Instruction fetch that is not executed
WB *: No operation is performed in the case of the JR instruction, and BR instruction but in
the case of the JARL instruction, data is written to the restore PC.
User’s Manual U12197EJ6V0UM
149