UPD703100 Datasheet, PDF (136/185 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 6 INTERRUPTS AND EXCEPTIONS
6.1.2 Non-maskable interrupt
A non-maskable interrupt cannot be disabled by an instruction and can therefore always be acknowledged. Non-
maskable interrupts of the V850 Series are generated by NMI input.
When the non-maskable interrupt is generated by NMI input, the processor performs the following steps, and
transfers control to the handler routine.
(1) Saves restore PC to FEPC.
(2) Saves current PSW to FEPSW.
(3) Writes exception code (0010H) to higher halfword of ECR (FECC).
(4) Sets NP and ID bits of PSW and clears EP bit.
(5) Sets handler address (00000010H) for the non-maskable interrupt to PC and transfers control.
Non-maskable interrupts are held pending in the interrupt controller INTC when another non-maskable interrupt is
currently being executed (when the NP bit of the PSW is 1). Non-maskable interrupts are enabled by resetting the
NP bit of the PSW to 0 with the RETI and LDSR instructions, which will enable servicing of a new or already pending
interrupt.
FEPC and FEPSW are used as the status saving registers.
Figure 6-2 illustrates how a non-maskable interrupt is serviced.
Figure 6-2. Non-Maskable Interrupt Servicing Format
INTC acknowledgement
CPU processing
NMI input
Non-maskable interrupt request
No
PSW.NP = 0
Yes
FEPC
FEPSW
ECR.FECC
PSW.NP
PSW.EP
PSW.ID
PC
Restored PC
PSW
0010H
1
0
1
00000010H
Interrupt request pending
Interrupt servicing
136
User’s Manual U12197EJ6V0UM