UPD780957 Datasheet, PDF (137/326 Pages) NEC – 8-Bit Single-Chip Microcontrollers

CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0
7.5.2 PPG output operation
Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in
Figure 7-10 allows operation as a programmable pulse generator (PPG) output.
A PPG output pulse is output from the TO0/TI00/P31 pin in a rectangular waveform, using the count value preset in
16-bit timer capture/compare register 00 (CR00) as the cycle and using the count value preset in 16-bit timer
capture/compare register 01 (CR01) as the pulse width.
Figure 7-10. Control Register Settings for PPG Output Operation
TMC0 0
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02
OVF0
0
0
0
1
1
0
0
Clear & start mode entered on
match between TM0 and CR00
CRC0 0
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
0
0
0
0
0
×
0
CR00 used as compare register
CR01 used as compare register
(c) 16-bit timer output control register 0 (TOC0)
TOC04 LVS0 LVR0 TOC01 TOE0
TOC0 0
0
0
1 0/1 0/1 1
1
TO0 output enable
Invert output on match between TM0 and CR00
Specify the initial value of TO0 output F/F
Invert output on match between TM0 and CR01
Cautions 1. When setting CR00 and CR01, be sure to satisfy the following expression.
0000H < CR01 < CR00 ≤ FFFFH
2. The cycle of the pulse generated by PPG output is “CR00 set value + 1”, and the duty is
(CR01 set value + 1)/(CR00 set value + 1).
Remark ×: don’t care
User’s Manual U13655EJ2V1UD
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