UPD17062 Datasheet, PDF (125/296 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY SYNTHESIZER AND IMAGE DISPLAY CONTROLLER

µPD17062
11.9.1 Interrupt Source Priorities
When using the multiple interrupt function, the priorities of interrupt sources must be determined.
For example, if the interrupt sources are A, B, C, and D, the following priorities can be specified:
A = B = C = D or A < B < C < D.
If A = B = C = D, the main routine always accepts interrupts A, B, C, and D. However, if interrupt C is accepted,
interrupts A, B, and D are inhibited, making the multiple interrupt function unusable.
If the priorities are A < B < C < D, interrupt C should be processed with the first priority even if interrupt
A or B is being processed. In this case, processing of interrupt D has the same priority as interrupt C.
The priorities can be set to hardware or software priorities by using the interrupt permission flags. Section
11.3 describes the hardware and software priorities.
To determine priorities at multiple interrupts, interrupt sources A and B are assumed have no priority and
source A is assumed to issue requests at 10 ms intervals. The interrupt processing time is assumed to be
4 ms. Source B is assumed to issue requests at 2 ms intervals. Lastly, the interrupt processing time is assumed
to be 1 ms.
Under these conditions, if interrupt A is issued by an interrupt request from A while interrupt B is being
processed, and the priorities of A and B are not determined, several interrupts from B will not be executed.
Because an interrupt is generally used for emergency processing, the A < B priority should be set in the
program to prevent interrupt A while interrupt B is being processed and accept interrupt B while interrupt A
is being processed.
When using the multiple interrupt function for non-emergency purposes, priorities need not be determined.
However, if the number of existing interrupt sources exceeds the multiple interrupt level limit described in
Section 11.9.2 or 11.9.3, be sure to determine priorities so that the interrupt level is not exceeded.
11.9.2 Interrupt Level Restriction by Interrupt Stack
The contents of the bank register of the system register and index enable flag are automatically saved in
the interrupt stack.
Fig. 11-7 (a) shows the interrupt stack operation.
The contents of all bank registers and index enable flags are reset when they are saved in the interrupt stack.
Because there are two levels of interrupt stacks, if multiple interrupts of more than two levels are issued,
the contents of the bank register and index enable flag are not restored normally as shown in Fig. 11-7 (b).
In other words, multiple interrupts of more than two levels cannot be used.
However, if the bank register and index enable flag are fixed in a main routine permits interrupts and
multiple interrupts have clear priorities as shown in Fig. 11-8, multiple interrupts of two levels or more can
be used by using subroutine return instruction RET.
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