UPD444016L Datasheet, PDF (10/16 Pages) NEC – 4M-BIT CMOS FAST SRAM 256K-WORD BY 16-BIT

µPD444016L
Write Cycle Timing Chart 2 (/CS Controlled)
Address (Input)
tAS
/CS (Input)
/WE (Input)
/LB, /UB (Input)
I/O (Input)
High impedance
tWC
tCW
tAW
tWP
tWR
tBW
tDW
Data in
tDH
High impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
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2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB
(or low level /UB).
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Data Sheet M14431EJ3V0DS