UPD703037A Datasheet, PDF (1/52 Pages) NEC – V850/SB2TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS

DATA SHEET
MOS INTEGRATED CIRCUITS
µPD703037A, 703037AY, 70F3037A, 70F3037AY
V850/SB2^TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD703037A, 703037AY, 70F3037A, and 70F3037AY (V850/SB2) are 32-/16-bit single-chip microcontrollers
of the V850 Family^TM for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial interfaces, A/D converter,
DMA controller, and so on are integrated on a single chip.
The µPD70F3037A and 70F3037AY have flash memory in place of the internal mask ROM of the µPD703037A
and 703037AY. Because flash memory allows the program to be written and erased electrically with the device
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale
production, and rapid development of new products.
The µPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, and 70F3035AY with different ROM/RAM
capacity are also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SB1^TM, V850/SB2 User’s Manual Hardware: U13850E
V850 Family User’s Manual Architecture:
U10243E
FEATURES
{ Number of instructions: 74
{ Minimum instruction execution time: 76.9 ns (@ internal 13 MHz operation)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,
load/store instructions
{ Memory space: 16 MB linear address space
{ Internal memory ROM: 512 KB (µPD703037A, 703037AY: mask ROM)
512 KB (µPD70F3037A, 70F3037AY: flash memory)
RAM: 24 KB (µPD703037A, 703037AY, 70F3037A, 70F3037AY)
{ Interrupt/exception: µPD703037A, 70F3037A, (external: 8, internal: 33 sources, exception: 1 source)
µPD703037AY, 70F3037AY (external: 8, internal: 34 sources, exception: 1 source)
{ I/O lines Total: 83
{ Timer/counters: 16-bit timer (2 channels: TM0, TM1)
8-bit timer (6 channels: TM2 to TM7)
{ Watch timer: 1 channel
{ Watchdog timer: 1 channel
{ IEBus controller: 1 channel
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14894EJ1V0DS00 (1st edition)
Date Published August 2000 J CP(K)
Printed in Japan
©
2000