N16D1633LPA Datasheet, PDF (5/27 Pages) NanoAmp Solutions, Inc. – 512K × 16 Bits × 2 Banks Low Power Synchronous DRAM

NanoAmp Solutions, Inc.
N16D1633LPA
Advance Information
Table 2: Pin Descriptions
PIN
CLK
CKE
/CS
A11
A0~A10
/RAS, /CAS, /WE
LDQM/UDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
PIN NAME
System Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTIONS
The system clock input. All other inputs are registered to the
SDRAM on the rising edge of the CLK
Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among power down, suspend
or self refresh.
Enable or disable all inputs except CLK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
Row Address : RA0~RA10
Column Address: CA0~CA7
Auto Precharge : A10
/RAS, /CAS and /WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in
write mode
Multiplexed data input/output pin
Power supply for internal circuits and input buffers
Power Supply for output buffers
No Connection
Stock No. 23395- Rev L 1/06
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.