N16D1633LPA Datasheet, PDF (19/27 Pages) NanoAmp Solutions, Inc. – 512K × 16 Bits × 2 Banks Low Power Synchronous DRAM

NanoAmp Solutions, Inc.
N16D1633LPA
Advance Information
Note :
1. H: Logic High, L: Logic Low, X: Don't care
2. For the given current state CKE must be low in the previous cycle.
3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
4. The address inputs depend on the command that is issued.
5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle
state.
6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down
mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained
for a minimum 100usec.
Stock No. 23395- Rev L 1/06
19
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.