N04L1618C2A Datasheet, PDF (5/10 Pages) NanoAmp Solutions, Inc. – 4Mb Ultra-Low Power Asynchronous CMOS SRAM 256Kx16 bit

NanoAmp Solutions, Inc.
N04L1618C2A
Power Savings with Page Mode Operation (WE = V_IH)
Page Address (A4 - A17)
Word Address (A0 - A3)
CE1
CE2
Word 1
Open page
Word 2
...
Word 16
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
(DOC# 14-02-016 REV G ECN# 01-1266)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.