MU9C8358L Datasheet, PDF (9/32 Pages) MUSIC Semiconductors – Quad 10/100Mb Ethernet Filter Interface

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MU9C8358L internal functions are shown in Figure 4.
Before discussing the individual blocks, the underlying
principles are presented. The network interfaces are
monitored for network and data symbol errors. Receive
data [RXD] is clocked into a register using the 25 MHz
recovered clock for 100Base-X or 2.5 MHz clock for
10Base-X. The Preamble and Start Frame delimiter (SFD)
are scanned to locate the Destination address (DA) and the
Source address (SA).
An addressing mechanism uniquely identifies each
MU9C8358L in a system. The Master MU9C8358L
schedules communication with the host processor and the
CAM through an arbitration process. Once the system is
initialized and configured, highest-priority is given to
network traffic.
The LANCTL block generates the command cycles and
operational codes to complete CPU-requested actions and
network-generated requests. The CPU must initialize the
CAM, write the permanent station list, and initiate other
housekeeping functions. Network traffic initiates DA
filtering, SA learning, and time stamp updates. All
state-machines required for real-time operations are
implemented in the ASIC hardware; the host CPU runs the
non-time-critical initialization routine.
Information on the LANCAM operation and instruction
set can be found in the appropriate LANCAM data sheet
for each device.
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Figure 4: MU9C8358L Functional Block Diagram