MU9C8358L Datasheet, PDF (14/32 Pages) MUSIC Semiconductors – Quad 10/100Mb Ethernet Filter Interface

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One set of registers is available to address up to two
MU9C8358L components and their attached LANCAMs
as a single system. The application decodes one range of
addresses to produce a Processor Chip Select System
signal (/PCSS) that is shared among all MU9C8358L
components. The lowest address in this
application-defined address range, shown in Table 3, is
referred to as SYSTEM_BASE.
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The System Status register (SSTAT) provides a CPU
visibility into the state of the LANCAM array. The /FF bit
indicates the current state of the Full Flag output of the
LANCAM array. The /MF bit indicates the Match Flag
output of the LANCAM array.
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The System Static Configuration register (SSTAT) allows
the CPU to configure the LANCAM array. These are set
and forget values. The CAM_SPD sets the controller to
match the speed grade of the LANCAM components
attached. A 50 MHz clock is assumed. The INV_REJ bit
configures all REJ ports A through D to be active LOW
instead of active HIGH.
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