TR8000 Datasheet, PDF (7/15 Pages) Murata Manufacturing Co., Ltd. – 916.5 MHz Hybrid Transceiver

Adress
0
1
2
Name
CFG0
CFG1
LoSyn
Bit 7
Sleep
-
Test
Bit 6
TX/RX
VCOlock
LOSyn6
Bit 5
ASK/OOK
-
LOSyn5
Bit 4
-
-
LOSyn4
Bit 3
Mode 1
BR3
LOSyn3
Bit 2
Mode 0
BR2
LOSyn2
Bit 1
-
BR1
LOSyn1
Bit 0
SV En
BR0
LOSyn0
Figure 3
CFG0 Bit 6 - When this bit is 0, the radio is in the receive mode (provided
CFG0 Bit 7 is 0). When this bit is 1, the radio is in one of the transmit
modes. Note the radio will transmit using OOK or ASK modulation,
depending on the value of CFG0 Bit 5. The power-on default value of this
bit is 0.
CFG0 Bit 5 - When this bit is 0, the transmitter uses OOK modulation.
When this bit is 1, the transmitter uses ASK modulation. The power-on
default value of this bit is 0.
CFG0 Bit 4 - This bit should always be set to 0 in the TR8000. The power-
on default value of this bit is 0.
CFG0 Bits 3, 2 - The states of these two bits set the basic operating mode
of the radio as shown below. The power-on default value of these two
bits is 0.
Bit 3
0
0
1
1
Bit 2
0
1
0
1
Mode
Single-channel Mode
Not Used
Not Used
Not Used
CFG0 Bit 1 - This bit should always be set to 0 in the TR8000. The power-
on default value of this bit is 0.
CFG0 Bit 0 - Setting this bit to logic 1 enables the internal start symbol
(vector) detection and the data and clock recovery circuit. When active,
this function continuously tests for a 16-bit start symbol, 0xE2E2 (hex).
Data clocking begins in the middle of the first bit following the 16-bit start
symbol, and clocking continues until CFG0 Bit 0 is reset to a logic 0. Note
that CFG0 Bit 0 must be set to back to a logic 1 to re-enable the start sym-
bol detection and the data and clock recovery circuit. The common way to
use this function is for the host processor to set this bit to a 1 when it is
ready to receive a message. When a start symbol is detected, data clock-
ing begins, and the host processor inputs the message bits. Once all of
the bits in the message are received, the host processor resets this bit to 0
to end data clocking. After the current message has been processed, the
host processor sets this bit to 1 again to enable detection of the next mes-
sage. The power-on default value of this bit is 0.
The start symbol pattern is sent starting with the MSB. This start symbol
pattern will not occur in a message that has been encoded for DC-balance
using either Manchester encoding or 8-to-12 bit symbolization using the
encoding table given below. Note that the table is given for 4-to-6 bit
encoding, so each byte of the message is encoded starting with the high
nibble and then the low nibble.
Nibble Hex Value
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Symbol Hex Value (6 bits)
0D
0E
13
15
16
19
1A
1C
23
25
26
29
2A
2C
32
34
CFG1 Bit 7 - This bit is unused in the TR8000.
CFG1 Bit 6 - This bit is a Read Only bit. Writing has no effect. When per-
forming a read and this bit is set, this indicates that the internal VCO is
locked and ready to transmit or receive data.
CFG1 Bit 5 - This bit is unused in the TR8000.
CFG1 Bit 4 - This bit is unused in the TR8000.
CFG1 Bits 3, 2, 1, 0 - These bits select the internal data and clock recov-
ery data (bit) rate as shown in the table below. The power-on default value
of these bits is 0.
LOSyn Bit 7 - This bit is only used in product testing. It should always be
set to 0 for normal operation. The power-on default value of this bit is 0.
LOSyn Bits 6, 5, 4, 3, 2, 1, 0 -These bits have no function in the TR8000
and can be written as either a logic 1 or a logic 0.
Note that data to/from the configuration registers is clocked in/out MSB
first. See the Control Register Read/Write Detail and Control Register
Read/Write Timing Drawings for additional details.
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TR8000-10182007
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