TR8000 Datasheet, PDF (5/15 Pages) Murata Manufacturing Co., Ltd. – 916.5 MHz Hybrid Transceiver

Power Down Control
TX CN CN CN
MOD TRL1 TRL0 FGR
R_TXM
8
17 18 19
Programming
and
Control
Antenna
RFIO
20
ESD
Choke
SAW
CR Filter
VCC1: Pin 2
VCC3: Pin 3
VCC2: Pin 16
GND1: Pin 1
GND2: Pin 10
TXA2 X
TXA1
RFA1
X
SAW
Delay Line
Temperature
Compensated
Master Oscillator
Local Oscillator,
Pulse Generator
& RF Amp Bias
15
3G ASH Transceiver Block Diagram
Log
RFA2
Detector
Low-Pass
Filter
BB
LPFADJ 9
R_LPF
AGC Set
Gain Select
AGC
Control
AGC Reset
BBOUT
Peak ^Ref
5
6
C_BBO
Detector
PKDET 4
C_PKD
DS2
dB Below
Peak Thld
AND
AGC
DS1
Ref
Thld
Threshold
Control
13
THLD1
R_TH1
11 12
THLD2
R_TH2
R_REF
Baud Rate
Selection
Data/Clock
RXDATA
Recovery 7
RXDCLK
14
Figure 2
Receiver Chain
The output of the SAW filter drives amplifier RFA1. This amplifier includes
provisions for detecting the onset of saturation (AGC Set), and for switch-
ing between 35 dB of gain and 5 dB of gain (Gain Select). AGC Set is an
input to the AGC Control function, and Gain Select is the AGC Control
function output. ON/OFF control to RFA1 (and RFA2) is generated by the
Pulse Generator & RF Amp Bias function. The output of RFA1 drives the
SAW delay line, which has a nominal delay of 0.5 µs.
The second amplifier, RFA2, provides 51 dB of gain below saturation. The
output of RFA2 drives a full-wave detector with 19 dB of threshold gain.
The onset of saturation in each section of RFA2 is detected and summed
to provide a logarithmic response. This is added to the output of the full-
wave detector to produce an overall detector response that is square law
for low signal levels, and transitions into a log response for high signal lev-
els. This combination provides excellent threshold sensitivity and more
than 70 dB of detector dynamic range. In combination with the 30 dB of
AGC range in RFA1, more than 100 dB of receiver dynamic range is
achieved.
The detector output drives a gyrator filter. The filter provides a three-pole,
0.05 degree equiripple low-pass response with excellent group delay flat-
ness and minimal pulse ringing. The 3 dB bandwidth of the filter can be set
from 4.5 kHz to 1.8 MHz with an external resistor.
The filter is followed by a base-band amplifier which boosts the detected
signal to the BBOUT pin with the receiver RF amplifiers operating at a
50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with a
peak-to-peak signal level of up to 450 mV. The detected signal is riding on
a 1.5 Vdc level that varies somewhat with supply voltage, temperature,
etc. BBOUT is coupled to the CMPIN pin, or to an external data recovery
process (DSP), by a series capacitor. The correct value of the series
capacitor depends on data rate, data run length, and other factors as dis-
cussed in the ASH Transceiver Designer’s Guide.
When an external data recovery process is used with AGC, BBOUT must
be coupled to the external data recovery process and to CMPIN by sepa-
rate series coupling capacitors. The AGC reset function is driven by the
signal applied to CMPIN.
Data Slicers
The CMPIN pin drives two data slicers, which convert the analog signal
from BBOUT back into a digital stream. The best data slicer configuration
depends on the system operating parameters. Data slicer DS1 is a capac-
itively-coupled comparator with provisions for an adjustable threshold.
DS1 provides the best performance at low signal-to-noise conditions. The
threshold, or squelch, offsets the comparator’s slicing level from 0 to 90
mV, and is set with a resistor between the RREF and THLD1 pins. This
threshold allows a trade-off between receiver sensitivity and output noise
density in the no-signal condition. For best sensitivity, the threshold is set
to zero but a minimum R_TH1 value of approximately 20 K Ohms should be
used for proper AGC action. In this case, noise is output continuously
when no signal is present. This, in turn, requires the circuit being driven by
the RXDATA pin to be able to process noise (and signals) continuously.
This can be a problem if RXDATA is driving a circuit that must sleep when
data is not present to conserve power, or when it its necessary to minimize
false interrupts to a multitasking processor. In this case, noise can be
greatly reduced by increasing the threshold level, but at the expense of
sensitivity. In order to guarantee THLD1 to be the value calculated, the
device should not be powered up in the receive mode. It should be pow-
ered up in either the sleep mode or the transmit mode and then switched
to the recieve mode. The best 3 dB bandwidth for the low-pass filter is also
affected by the threshold level setting of DS1. The bandwidth must be
increased as the threshold is increased to minimize data pulse-width vari-
ations with signal amplitude.
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TR8000-10182007
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