OP4012B Datasheet, PDF (4/7 Pages) RF Monolithics, Inc – 644.53125 MHz Optical Timing Clock

Differential Output Symmetry - for balanced output loads, the differential output symmetry of the OP4012B is ±1%.
This differential output symmetry meets the requirements of the most demanding high-speed logic families.
Output DC Voltage Configurability - the OP4012B differential outputs can be DC-configured to support a wide range of high-speed logic families and ASIC
drive requirements by the selection of four resistors (see Configuring the OP4012B DC Output Voltage below) and a logic supply voltage. Each differential
output of the OP4012B is AC-coupled to provide this flexibility.
OP4005B Tuning Details
The frequency tuning of the OP4012B is characterized over a voltage range of 0 to 3.3 V. The tuning voltage applied to the OP4012B should be limited to
this range. Figure 4 shows the typical locked tuning range for operation over -40 or +85 °C. The frequency shift of a quartz SAW frequency control device
with temperature has the shape of an inverted parabola, with the highest frequency occurring around +25 °C. At both -40 and +85 °C, there will be a 170
ppm downward shift in the frequency of the SAW device compared to +25 °C. Tuning to compensate for this temperature shift is the same as tuning
170 ppm higher at +25 °C. This is well within the tuning range of the OP4012B, as shown in Figure 4. Note that the voltage tuning constant, K_V, is bounded
between 140 and 300 ppm/V under locked conditions for any temperature within the OP4012B's specified operating range.
The OP4012B tuning port presents a input impedance greater than 100 kilohms from DC to 50 kHz, and at least 1 kilohm for any RF frequency up to the
operating frequency of the OP4012B. Most operational amplifiers used in active loop filters will be stable when driving the tuning port directly. Special care
are should be taken to avoid ground loops in the path from the output of the phase detector though the loop filter to the tuning input of the OP4012B. For
most applications, the bandwidth of the loop filter in a OP4012B PLL will be less than 50 Hz, as discussed in the example OP4012B PLL application section
below.
Configuring the OP4012B DC Output Voltage
Each differential output of the OP4012B is AC coupled, allowing the static DC level at each output to be set with a resistive divider to match the logic family
being driven by the clock. The parallel-equivalent resistance of the two resistors in each divider should be approximately 50 ohms. The supply voltage to
the dividers, V_LOAD, should be two to three times the value of the static DC voltage, V_DC.
Referring to the accompanying figure:
V_DC = V_LOAD*R1/(R1 + R2)
and
50 = R1*R2/(R1 + R2)
OP4012B DC Output Voltage Adjustment
3.3 Vdc
V_LOAD
The values of the resistors R2 and
R1 are given directly as:
R2 = 50*V_LOAD/V_DC
R1 = 1/(0.02 - (1/R2))
R2
V_TUNE
OP4012B
R1
R2
V_DC
Load
V_DC
R1
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