OP4012B Datasheet, PDF (1/7 Pages) RF Monolithics, Inc – 644.53125 MHz Optical Timing Clock

• Quartz SAW Stabilized Differential Output Technology
• Very Low Jitter Fundamental-Mode Operation at 644.53125 MHz
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• Voltage Tunable for Phase Locked Loop Applications
• Timing Reference for 10G Optical Ethernet Communications Systems
• Complies with Directive 2002/95/EC (RoHS)
The OP4012B is a voltage-controlled SAW clock (VCSC) designed for phase-locked loop (PLL) applications
in optical data communications systems. The differential outputs of the OP4012B are generated by high-Q,
fundamental mode quartz surface acoustic wave (SAW) technology. This technique provides very low output
jitter and phase noise, plus excellent immunity to power supply noise. The OP4012B differential outputs
feature ±1% symmetry, and can be DC-configured to drive a wide range of high-speed logic families. The
OP4012B is packaged in a hermetic metal-ceramic LCC.
Absolute Maximum Ratings
Rating
Value
Units
DC Suppy Voltage
Tuning Voltage
0 to 5.5
Vdc
0 to 5.5
Vdc
Case Temperature
-55 to 100
°C
OP4012B
644.53125 MHz
Optical
Timing Clock
SMC-08
Electrical Characteristics
Characteristic
Operating Frequency Absolute Frequency
Tuning Range
Tuning Voltage
Tuning Linearity
Tuning Sensitivity
Modulation Bandwidth
Q and Q Output
Voltage into 50 Ω (VSWR<1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
Phase Noise
@ 100 Hz offset
@ 1 kHz offset
@ 10 kHz offset
Noise Floor
Q and Q Jitter
RMS Jitter
No Noise on V_CC
200 mV_P-P Noise, from 1 MHz to ½ f_O on V_CC
Input Impedence (Tuning Port)
Output DC Resistance (between Q & Q)
DC Power Supply
Operating Voltage
Operating Current
Operating Case Temperature
Lid Symbolization (YY=Year, WW=Week)
Sym
f_O
df/dv
V_O
V_CC
I_CC
T_C
Notes
1
2
1
1, 8
2
1,3
1,3
3, 4, 5
3, 4, 6
3, 4, 6, 7
3, 6
3, 6
3, 6
3, 6
3, 4, 6, 7
3, 4, 6, 7
3
1, 3
1, 3
1, 3
1, 3
Minimum
±100
0
100
125
0.60
Typical
644.53125
±5
265
49
1
50
3.13
-70
-100
-125
-150
2
12
12
3.3 or 5.0
-40
RFM OP4012B YYWW
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
COCOM CAUTION: Approval by the U.S. Department of Commerce is required prior to export of this device.
Maximum
3.3
260
1.1
2:1
51
-30
-60
5.25
70
+85
Units
MHz
ppm
V
%
ppm/V
kHz
V_P-P
%
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
ps_P-P
ps_P-P
KΩ
KΩ
Vdc
mA
°C
Notes:
1. Unless otherwise noted, all specifications include the combined effects of load VSWR, V_CC and T_C.
2. Net tuning range after tuning out the effects of initial manufacturing tolerances, VSWR pushing/pulling, V_CC, T_C and aging.
3. The internal design, manufacturing processes, and specifications of this device are subject to change without notice.
4. Specified only for a balanced load with a VSWR < 1.2 ( 50 ohms each side), and a V_CC = 3.0 Vdc.
5. Symmetry is defined as the width in (% of total period) measure at 50% of the peak-to-peak voltage of either output.
6. Jitter and other noise outputs due to power supply noise or mechanical vibration are not included in this specification except where noted.
7. Applies to period jitter of either differential output. Measured with a Tektronix CSA803 signal analyzer with at least 1000 sample.
8. One or more of the following United States patents apply: 4, 616,197; 4,670,681; 4,760,352.
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©2008-2010 by RF Monolithics, Inc.
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OP4012B - 2/4/10