SCC1300-D04 Datasheet, PDF (28/34 Pages) Murata Manufacturing Co., Ltd. – Combined Gyroscope and 3-axis Accelerometer with digital SPI interfaces

SCC1300-D04
5.5 Accelerometer ASIC Addressing Space
The SCC1300 accelerometer ASIC register contents and bit definitions are described in detail in
the following sections.
Table 15. Accelerometer register address space
Address
Register Name Bits
Read/ Description
hex
01h
CTRL
Write
7:0 R/W Please refer to Table 16 for CTRL register details.
02h
STATUS
7:2
R Reserved
1
R CSMERR: EEPROM checksum error
1 – Error,
0 – No error
CSMERR also sets ST bit in SPI frame
0
R FRME: SPI frame error. Bit is reset when next correct SPI
frame is received.
FRME also sets FRME bit in SPI frame
03h
RESET
7:0 R/W Writing 0C'hex, 05'hex, 0F'hex in this order resets component
04h
X_LSB
7:0
R X-axis LSB data frame (Read always X_MSB prior to X_LSB)
05h
X_MSB
7:0
R X-axis MSB data bits (Reading of this register latches X_LSB)
06h
Y_LSB
7:0
R Y-axis LSB data frame (Read always Y_MSB prior to Y_LSB)
07h
Y_MSB
7:0
R Y-axis MSB data bits (Reading of this register latches Y_LSB)
08h
Z_LSB
7:0
R Z-axis LSB data frame (Read always Z_MSB prior to Z_LSB)
09h
Z_MSB
7:0
R Z-axis MSB data bits (Reading of this register latches Z_LSB)
12h
TEMP_LSB
7:0
R Data bits [7:0] of temperature sensor
Always read TEMP_MSB prior to TEMP_LSB
13h
TEMP_MSB
7:0
R Data bits [15:8] of temperature sensor
Reading of this register latches TEMP_LSB
16h
INT_STATUS
7
R Reserved
6
R SAT: Saturation status of output data
1 – Over range detected, at least one of XYZ axis is saturated
and output data is not valid.
0 – Data in range
SAT bit is also visible in SPI frame. This bit can be active after
start-up, reset or PORST stage before signal path settles to
final value. If accelerometer self diagnostics is used follow
power-up sequence to acknowledge this bit (Table 11).
5
R STS: Status of gravitation based start-up self test
1 – Failure
0 – No failure
STS also sets ST bit in SPI frame
4
R STC: Status of continuous self test
1 – Failure
0 – No failure
STC also sets ST bit in SPI frame
3:0
R Reserved
27h
ID
7:0
R Customer readable component identification number, value
90h
Note: INT_STATUS: The bits in the interrupt status register and the corresponding SPI frame bits are cleared after this
register has been read. Register reading is treated as interrupt acknowledgement signal. Bits in this register are kept
active even if the failure condition is over until they are acknowledged by reading the register.
Murata Electronics Oy
www.muratamems.fi
Subject to changes
Doc.Nr. 82113100
28/34
Rev. D