SCC1300-D04 Datasheet, PDF (23/34 Pages) Murata Manufacturing Co., Ltd. – Combined Gyroscope and 3-axis Accelerometer with digital SPI interfaces

SCC1300-D04
5.4 Accelerometer Interface
This chapter describes the SCC1300 accelerometer sensor ASIC interface and how to use it. The
accelerometer sensor ASIC SPI interface uses 8-bit addressing.
5.4.1 Accelerometer SPI Communication Overview
Each communication frame contains 16 bits (two 8-bit bytes). The SPI frame format and transfer
protocol for the accelerometer is presented in Figure 13 below. The accelerometer captures data
on the SCK's rising edge (MOSI line) and data is propagated on the SCK’s falling edge (MISO
line). This is equal to SPI Mode 0 (CPOL = 0 and CPHA = 0). The SPI transmission is always
started with the CSB falling edge and terminated with the CSB rising edge.
Figure 13. SPI frame format for the accelerometer interface
• MOSI
• A5:A0
Register address
• R/W
Read/Write selection, '0' = read, ‘1’ = write
• aPAR
Odd parity for bits A5:A0, R/W
• DI7:DI0
Input data for data write
• MISO
• Bit 1
Not defined
• FRME
FRaMe Error indication (from previous frame)
• Bit 3-5 status bits
• PORST Power On Reset Status
• ST
Self Test error
• SAT Output SATuration indicator
• Bit 6
Fixed bit, always ‘0’
• Bit 7
Fixed bit, always ‘1’
• dPAR
Odd parity for output data (DO7:DO0)
• DO7:DO0
Output data
The first 8 bits in the MOSI line contain info about the operation (read/write) and the register
address being accessed. The first 6 bits form an address field for the selected operation, which is
defined by bit 7 (‘0’ = read ‘1’ = write) and is followed by an odd parity bit (aPAR) for the address.
The following 8 bits in the MOSI line contain data for the write operation and are ignored in case
of a read operation.
The first bits in the MISO line are the Frame Error bit of the previous frame (FRME), the Power
On Reset STatus bit (PORST), the Self-Test status bit (ST), the Saturation status bit (SAT), the
fixed zero bit, the fixed one bit and the Odd Parity bit for output data (dPAR). Parity is calculated
from data that is currently being sent. The following 8 bits contain data for a read operation.
During a write operation, these data bits are the previous data bits of the addressed register.
For write commands, data is written into the addressed register on the rising edge of the CSB. If
the command frame is invalid, data will not be written into the register.
Murata Electronics Oy
www.muratamems.fi
Subject to changes
Doc.Nr. 82113100
23/34
Rev. D