ADCDS-1403 Datasheet, PDF (6/9 Pages) C&D Technologies – 14-Bit, 3 Megapixels/Second Imaging Signal Processor

Out-of-Range Indicator
The ADCDS-1403 provides a digital Out-of-Range output
signal (pin 24) for situations when the video input signal (saturated signal)
is beyond the input range of the internal A/D converter. The digital output
bits and the Out-of-Range signal correspond to a particular sampled video
input voltage, with both of these signals having a common pipeline delay.
Using the circuit described in Figure 8., both overrange and under-
range conditions can be detected (see Table 1). When combined with a D/A
converter, digital detection and orrection can be performed for both the gain
and offset errors.
MSB
OUT-OF-RANGE
"OVERRANGE"
"UNDERRANGE"
Figure 8. Overrange/ Underrange Circuit
OUT OF
RANGE
0
0
1
1
Table 1. Out-of-Range Conditions
OVER
MSB
UNDER RANGE
RANGE
0
0
0
1
0
0
0
0
1
1
1
0
INPUT SIGNAL
In Range
In Range
Underrrange
Overrange
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Output Coding
The ADCDS-1403's output coding is Straight Binary as indicated in
Table 2. The table shows the relationship between the output data coding
and the difference between the reference signal voltage and its correspond-
ing video signal voltage. (These voltages are referred to the output of the
ADCDS-1403's input amplifier's VOUT).
Programmable Analog Bandwidth Function
When interfacing to CCD arrays with very high-speed "read-out" rates,
the ADCDS-1403's input stage must have sufficient analog bandwidth to
accurately reproduce the output signals of the CCD array. The amount of
analog bandwidth determines how quickly and accurately the "Reference
Hold" and the "CDS output" signals will settle. If only a single analog band-
width was offered, the ADCDS-1403's bandwidth would be set to acquire
and digitize CCD output signals to 14-bit accuracy, at maximum conversion
rate of 3MHz (333ns see Figure 11. for details). Applications not requiring
the maximum conversion rate would be forced to use the full analog band-
width at the possible expense of noise performance.
The ADCDS-1403 avoids this situation by offering a fully programmable
analog bandwidth function. The ADCDS-1403 allows the user to "bandwidth
limit" the input stage in order to realize the highest level of noise perfor-
mance for the application being considered. Table 3. describes how to select
the appropriate reference hold "aquisition time" and CDS output "settling
time" needed for a particular application. Each of the selections listed in
Table 3. have been optimized to provide only enough analog bandwidth to
acquire a full scale input step, to 14-bit accuracy, in a single conversion.
Increasing the analog bandwidth (using a faster settling and acquisition
time) would only serve to potentially increase the amount of noise at the
ADCDS-1403's output. The ADCDS-1403 uses a two bit digital word to
select four different analog bandwidths for the ADCDS-1403's input stage
(See Table 3. for details).
Table 2. Output Coding
INPUT AMPLIFIER VOUT, ➀ (VOLTS P-P)
Video Signal-Reference Signal
> –2.80000
–2.80000
–2.10000
–1.40000
–0.70000
–0.35000
–0.000171
0
Video Signal-Reference Signal
<0➁
SCALE
>Full Scale –1LSB
Full Scale –1LSB
3/4FS
1/2FS
1/4FS
1/8FS
1 LSB
0
<0
DIGITAL OUTPUT
11 1111 1111 1111
11 1111 1111 1111
11 0000 0000 0000
10 0000 0000 0000
01 0000 0000 0000
00 1000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
Notes:
➀ Input Amplifier VOUT = (Video Signal - Reference Level)
➁ The video portion of the differential signal (input-amplifier's VOUT) must be more negative than its associated reference
level and VOUT should not exceed ±2.8V DC.
OUT-OF-RANGE
1
0
0
0
0
0
0
0
1
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